Trenched semiconductor devices and their manufacture

• US 7,033,889 B2
• Filed: 09/02/2005
• Issued: 04/25/2006
• Est. Priority Date: 12/08/2001
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hijzen, Erwin A., Hueting, Raymond J. E., In 't Zandt, Michael A. A.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US11/220,297
• Publication Number:
  US 20060008991A1
• Time in Patent Office: 235 Days
• Field of Search: 438/259, 438/270, 438/271, 438/272, 438/589, 438/619
• US Class Current: 438/259
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

Claims

1. A method of forming a semiconductor device including an insulated trench electrode in a trench, the trench extending through a semiconductor body portion of the device, and the trench electrode being dielectrically coupled to the body portion by an insulating layer at a side-wall of the trench, the method including the steps of:

(a) etching a trench into the body portion;

(b) providing a layer of filler material over the bottom of the trench;

(c) providing trench electrode material in the trench with a path defined through the trench electrode material to the underlying filler material;

(d) etching to remove filler material between the trench electrode material and the bottom of the trench; and

(e) closing the path through the trench electrode material to leave a cavity between the trench electrode material and the bottom of the trench, which cavity reduces the dielectric coupling between the trench electrode and the body portion at the bottom of the trench.

2. A method of claim 1 wherein step (c) comprises forming spacers of trench electrode material over opposing side-walls of the trench.

3. A method of claim 1 wherein step (e) comprises oxidising the trench electrode material to grow oxide spanning the path.

4. A method of claim 1, wherein the filler material is the same as that of the trench electrode insulating layer.

5. A method of claim 1, wherein the filler material is selectively etchable with respect to that of the trench electrode insulating layer.

6. A method of forming a semiconductor device of claim 1, wherein the cavity is defined by the deposition of the trench electrode material.