Trench gate laterally diffused MOSFET devices and methods for making such devices

• US 7,033,891 B2
• Filed: 10/03/2002
• Issued: 04/25/2006
• Est. Priority Date: 10/03/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Wilson, Peter H., Thornton, Neill, Sapp, Steven
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US10/269,126
• Publication Number:
  US 20040065919A1
• Time in Patent Office: 1,300 Days
• Field of Search: 257/343, 257/329, 257/330, 257/331, 438/270, 438/271, 438/272, 438/259, 438/212
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices is described. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.

Claims

1. A method for making a MOSFET, comprising:

providing a substrate including an epitaxial layer;

forming a first trench in the epitaxial layer;

filling the first trench with an insulating layer;

forming a second trench in the insulating layer such that the second trench is not symmetric relative to the first trench;

filling the second trench with a conductive material; and

forming a plurality of dopant regions adjacent the first trench with a first one of the plurality of dopant regions extending under the first trench.

2. The method of claim 1 further comprising forming the plurality of dopant regions within the epitaxial layer.

3. The method of claim 2 wherein a second one of the plurality of dopant regions is formed adjacent the first one of the plurality of dopant regions, the second one of the plurality of dopant regions having a higher dopant concentration than the first one of the plurality of dopant regions.

4. The method of claim 3 wherein the substrate and the epitaxial layer are of a first conductivity type, and the first one of the plurality of dopant regions and the second one of the plurality of dopant regions are of a second conductivity type.

5. A method for making a MOSFET, comprising:

providing a substrate having an epitaxial layer thereon;

forming a first trench in the epitaxial layer;

filling the first trench with an oxide layer;

forming a second trench in the oxide layer so that the second trench is not symmetric relative to the first trench;

filling the second trench with a conductive material; and

forming a plurality of dopant regions adjacent the first trench and within the epitaxial layer, wherein the plurality of dopant regions contains a first dopant region extending under the first trench and a second dopant region with a dopant concentration higher than the first dopant region.

6. The method of claim 5 wherein the substrate and the epitaxial layer are of a first conductivity type and the first and second dopant regions are of a second conductivity type.

7. A method of forming a MOSFET, comprising:

forming a first trench in a silicon region extending over a substrate, the silicon region and the substrate being of a first conductivity type but having different doping concentrations;

filling the first trench with an insulating layer;

forming a second trench in the insulating layer, the second trench being asymmetrical relative to the first trench such that a spacing between a first sidewall of the first trench and a corresponding first sidewall of the second trench is different than a spacing between a second sidewall of the first trench and a corresponding second sidewall of the second trench;

forming a conductive material in the second trench; and

forming a first drift region of a second conductivity type in the silicon region, the first drift region extending under the first trench.

8. The method of claim 7 further comprising:

forming second and third drift regions of the second conductivity type in the silicon region, the second drift region separating the third drift region from the first trench.

9. The method of claim 8 wherein the first, second, and third drift regions are contiguous, the second drift region having a higher doping concentration than the first drift region, and the third drift region having a higher doping concentration than the second drift region.

10. The method of claim 7 wherein the remaining portion of the insulating layer after forming the second trench is thicker along a bottom of the first trench than along one of the sidewalls of the first trench.

11. The method of claim 7 wherein the remaining portion of the insulating layer after forming the second trench is thicker along a first sidewall of the first trench than along a second sidewall of the first trench opposing the first sidewall.

12. The method of claim 7 wherein the silicon region is an epitaxial layer, the method further comprising:

forming the epitaxial layer over the substrate.

13. A MOSFET comprising:

a first silicon region of a first conductivity type;

a gate trench extending into the first silicon region, the gate trench having an asymmetric insulating layer along two of its opposing sidewalls;

a source region having a dopant region of a second conductivity type, the dopant region laterally extending along one side of the gate trench to contact a source electrode; and

a lightly doped drain region of the second conductivity type laterally extending below and along an opposing side of said one side of the gate trench to contact a drain electrode,

wherein a spacing between the drain electrode and the gate trench is greater than a corresponding spacing between the source electrode and the gate trench.

14. The MOSFET of claim 13 wherein the lightly doped drain region partially extends up along a first sidewall of the gate trench such that a channel region along the first sidewall between the source region and the lightly doped drain region extends along only the vertical dimension.

15. The MOSFET of claim 13 wherein the lightly doped drain region comprises at least first and second drift regions, the second drift region being laterally separated from the gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region.

16. The MOSFET of claim 13 wherein the asymmetric insulating layer extends along a bottom of the trench, the asymmetric insulating layer being thicker along the bottom of the gate trench than along the sidewall of the gate trench adjacent the source region.

17. The MOSFET of claim 13 wherein the asymmetric insulating layer is thicker along the sidewall of the gate trench adjacent the lightly doped drain region than along the sidewall of the gate trench adjacent the source region.

18. The MOSFET of claim 13 being configured such that in the on state a conduction channel is formed along the sidewall of the gate trench adjacent the source region while no conduction channel is formed along the sidewall of the gate trench adjacent the lightly doped drain region.

19. The MOSFET of claim 13 wherein the first silicon region is an epitaxial layer over a substrate, the dopant region in the source region and the epitaxial layer being electrically connected together so as to be biased to the same potential.

20. The MOSFET of claim 13 wherein the MOSFET is a radio frequency MOSFET.

21. A MOSFET comprising:

a first silicon region of a first conductivity type;

a gate trench extending into the first silicon region, the gate trench having an asymmetric insulating layer along two of its opposing sidewalls;

a source region having a dopant region of a second conductivity type, the dopant region laterally extending along one side of the gate trench to contact a source electrode; and

a lightly doped drain region of the second conductivity type laterally extending below and along an opposing side of said one side of the gate trench to contact a drain electrode, the lightly doped drain region comprising at least first and second drift regions, the second drift region being laterally separated from the gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region.

22. The MOSFET of claim 21 wherein the lightly doped drain region partially extends up along a first sidewall of the gate trench such that a channel region along the first sidewall between the source region and the lightly doped drain region extends only along the vertical dimension.

23. The MOSFET of claim 21 wherein a spacing between the drain electrode and the gate trench is greater than a corresponding spacing between the source electrode and the gate trench.

24. The MOSFET of claim 21 wherein the asymmetric insulating layer extends along a bottom of the gate trench, the asymmetric insulating layer being thicker along the bottom of the gate trench than along the sidewall of the gate trench adjacent the source region.

25. The MOSFET of claim 21 wherein the asymmetric insulating layer is thicker along the sidewall of the gate trench adjacent the lightly doped drain region than along the sidewall of the gate trench adjacent the source region.

26. The MOSFET of claim 21 being configured such that in the on state a conduction channel is formed along the sidewall of the gate trench adjacent the source region while no conduction channel is formed along the sidewall of the gate trench adjacent the lightly doped drain region.

27. The MOSFET of claim 21 wherein the first silicon region is an epitaxial layer over a substrate, the dopant region in the source region and the epitaxial layer being electrically connected together so as to be biased to the same potential.

28. A MOSFET comprising:

an epitaxial layer of a first conductivity type over a substrate;

a gate trench extending into the epitaxial layer, the gate trench having an asymmetric insulating layer along two of its opposing sidewalls;

a source region having a dopant region of a second conductivity type in the epitaxial layer, the dopant region laterally extending along one side of the gate trench to contact a source electrode; and

a lightly doped drain region of the second conductivity type laterally extending below and along an opposing side of said one side of the gate trench to contact a drain electrode, the lightly doped drain region comprising at least first and second drift regions, the second drift region being laterally separated from the gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region,

wherein a spacing between the drain electrode and the gate trench is greater than a corresponding spacing between the source electrode and the gate trench.

29. The MOSFET of claim 28 wherein the asymmetric insulating layer extends along a bottom of the trench, the asymmetric insulating layer being thicker along the bottom of the gate trench than along the sidewall of the gate trench adjacent the source region.

30. The MOSFET of claim 28 wherein the asymmetric insulating layer is thicker along the sidewall of the gate trench adjacent the lightly doped drain region than along the sidewall of the gate trench adjacent the source region.

31. The MOSFET of claim 28 being configured such that in the on state a conduction channel is formed along the sidewall of the gate trench adjacent the source region while no conduction channel is formed along the sidewall of the gate trench adjacent the lightly doped drain region or along a bottom of the gate trench.

32. A MOSFET comprising:

a first silicon region of a first conductivity type;

first and second gate trenches extending into the first silicon region, the first gate trench having an asymmetric insulating layer along two of its opposing sidewalls, the second gate trench having a symmetric insulating layer along two of its opposing sidewalls;

a plurality of dopant regions in the first silicon region, a first one of the plurality of dopant regions having a second conductivity type and laterally extending along one side of the second gate trench to contact a source electrode, and a second one of the plurality of dopant regions of the second conductivity type separating the first and second gate trenches; and

a lightly doped drain region of the second conductivity type laterally extending along one side of the first gate trench to contact a drain electrode, the lightly doped drain region further extending below both the first and second gate trenches.

33. The MOSFET of claim 32 wherein the lightly doped drain region comprises at least first and second drift regions, the second drift region being laterally separated from the first gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region.

34. The MOSFET of claim 32 wherein the lightly doped drain region partially extends up along a first sidewall of the second gate trench such that a channel region along the first sidewall between the first one of the plurality of dopant regions and the lightly doped drain region extends only along the vertical dimension.

35. The MOSFET of claim 32 wherein a spacing between the drain electrode and the first gate trench is greater than a spacing between the source electrode and the second gate trench.

36. The MOSFET of claim 32 wherein:

the symmetric insulating layer extends along a bottom of the second gate trench, the symmetric insulating layer being thicker along the bottom of the second gate trench than along the sidewalls of the second gate trench, and

the asymmetric insulating layer extends along a bottom of the first gate trench, the asymmetric insulating layer being thicker along the bottom of the first gate trench than along a sidewall of the first gate trench adjacent the second one of the plurality of dopant regions.

37. The MOSFET of claim 32 wherein the asymmetric insulating layer is thicker along a sidewall of the first gate trench adjacent the lightly doped drain region than along a sidewall of the first gate trench adjacent the second one of the plurality of dopant regions.

38. The MOSFET of claim 32 being configured such that in the on state a conduction channel is formed along those sidewalls of the first and second gate trenches adjacent the first one and second one of the plurality of dopant regions while no conduction channel is formed along a sidewall of the first gate trench adjacent the lightly doped drain region.

39. The MOSFET of claim 32 wherein the first silicon region is an epitaxial layer over a substrate.