Digital interface for driving at least a couple of power elements, in particular in PWM applications

• US 7,034,479 B2
• Filed: 12/24/2003
• Issued: 04/25/2006
• Est. Priority Date: 12/24/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Bombaci, Francesco, Inglese, Alessandro
• Primary Examiner(s): Ro, Bentsu
• Application Number:
  US10/746,118
• Publication Number:
  US 20040218409A1
• Time in Patent Office: 853 Days
• Field of Search: 318/254, 318/293, 318/445, 318/452, 318/484, 318/722, 318/801, 363/56.02, 363/58, 363/98, 363/56.04, 363/58.98, 327108-112, 307139-141, 307/141.8
• US Class Current: 318/293
• CPC Class Codes: H02M 7/53873 with digital control

Abstract

A digital interface for driving at least one complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references is provided. The digital interface includes a first input terminal for receiving a PWM input signal, a first counter stage connected to the first input terminal, and a second counter stage connected to an output of the first counter stage. A toggle stage is connected to the first input terminal and to an output of the second counter stage. A first output terminal is connected to an output of the toggle stage, and is to be connected to a control terminal of the first power element. A second output terminal is connected to the output of the first counter stage for receiving a delayed PWM output signal therefrom, and is to be connected to a control terminal of the second power element. The toggle stage generates a second PWM output signal for the first output terminal. The second PWM output signal is kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.

Claims

1. A digital interface for driving at least one complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references, the digital interface comprising:

a first input terminal for receiving a PWM input signal;

a first counter stage connected to the first input terminal;

a second counter stage connected to an output of the first counter stage;

a toggle stage connected to the first input terminal and to an output of the second counter stage;

a first output terminal connected to an output of the toggle stage, and to be connected to a control terminal of the first power element; and

a second output terminal connected to the output of the first counter stage for receiving a delayed PWM output signal therefrom, and to be connected to a control terminal of the second power element;

the toggle stage generating a second PWM output signal for the first output terminal, the second PWM output signal being kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.

2. A digital interface according to claim 1, wherein the first and second counter stages and the toggle stage are synchronized by a same clock signal.

3. A digital interface according to claim 2, wherein the predetermined duration corresponds to 2N times a period of the clock signal.

4. A digital interface according to claim 3, wherein the toggle stage comprises a state machine.

5. A digital interface according to claim 4, wherein the state machine has the following sequence of operating states:

changing from a first inactive state to a second wait state based upon a low-high transition of the PWM input signal;

changing from the second wait state to a third low logic level state based upon a low-high transition of a delayed signal generated by the second counter stage and delayed by N times the clock period;

changing from the third low logic level state to a fourth transition state based upon a high-low transition of the PWM input signal;

changing from the fourth transition state back to the first inactive state based upon a high-low transition of the delayed signal; and

the second PWM output signal performing a low-high transition delayed by 2N times the clock period with respect to the high-low transition of the PWM input signal when the state machine goes back to the first inactive state.

6. A digital interface according to claim 5, wherein the state machine further has the following sequence of operating states:

changing from the third low logic level state to the fourth transition state based upon a high-low transition of the PWM input signal preceding the high-low transition of the delayed signal;

changing from the fourth transition state to a fifth low logic level state based upon a low-high transition of the PWM input signal;

changing from the fifth low logic level state to the second wait state based upon a high-low transition of the delayed signal;

changing from the second wait state to the third low logic level state based upon a low-high transition of the delayed signal;

changing from the third low logic level state to the fourth transition state based upon a low level of the input signal;

changing from the fourth transition state back to the first inactive state based upon a high-low transition of the delayed signal; and

when the state machine changes back to the first inactive state, the second output signal performing a low-high transition delayed by 2N times the clock period with respect to the high-low transition of the PWM input signal, the second output signal being kept at a low level during the high-low-high transition of the input signal which is lower than the predetermined duration.

7. A digital interface according to claim 6, wherein the state machine changes from the third low logic level state to the first inactive state based upon a high-low transition of the delayed signal immediately following a low-high transition of the delayed signal.

8. A digital interface according to claim 1, wherein the first and second counter stages and the toggle stage receive a same set signal and a same reset signal.

9. A control system for an electrical motor comprising:

a driving stage to be connected to the electrical motor and comprising a complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references; and

a digital interface connected to the driving stage and comprising

a first input terminal for receiving a PWM input signal,

a first counter stage having an input connected to the first input terminal and an output providing a delayed PWM output signal to a control terminal of the second power element,

a second counter stage having an input connected to the output of the first counter stage, and

a toggle stage having inputs connected to the first input terminal and to an output of the second counter stage, and an output connected to a control terminal of the first power element for providing a second PWM output signal, the second PWM output signal being kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.

10. A control system according to claim 9, wherein the first and second counter stages and the toggle stage are synchronized by a same clock signal.

11. A control system according to claim 10, wherein the predetermined duration corresponds to 2N times a period of the clock signal.

12. A control system according to claim 11, wherein the toggle stage comprises a state machine.

13. A control system according to claim 12, wherein the state machine has the following sequence of operating states:

changing from a first inactive state to a second wait state based upon a low-high transition of the PWM input signal;

changing from the second wait state to a third low logic level state based upon a low-high transition of a delayed signal generated by the second counter stage and delayed by N times the clock period;

changing from the third low logic level state to a fourth transition state based upon a high-low transition of the PWM input signal;

changing from the fourth transition state back to the first inactive state based upon a high-low transition of the delayed signal; and

the second PWM output signal performing a low-high transition delayed by 2N times the clock period with respect to the high-low transition of the PWM input signal when the state machine goes back to the first inactive state.

14. A control system according to claim 13, wherein the state machine further has the following sequence of operating states:

changing from the third low logic level state to the fourth transition state based upon a high-low transition of the PWM input signal preceding the high-low transition of the delayed signal;

changing from the fourth transition state to a fifth low logic level state based upon a low-high transition of the PWM input signal;

changing from the fifth low logic level state to the second wait state based upon a high-low transition of the delayed signal;

changing from the second wait state to the third low logic level state based upon a low-high transition of the delayed signal;

changing from the third low logic level state to the fourth transition state based upon a low level of the input signal;

changing from the fourth transition state back to the first inactive state based upon a high-low transition of the delayed signal; and

when the state machine changes back to the first inactive state, the second output signal performing a low-high transition delayed by 2N times the clock period with respect to the high-low transition of the PWM input signal, the second output signal being kept at a low level during the high-low-high transition of the input signal which is lower than the predetermined duration.

15. A control system according to claim 14, wherein the state machine changes from the third low logic level state to the first inactivity state based upon a high-low transition of the delayed signal immediately following a low-high transition of the delayed signal.

16. A control system according to claim 9, wherein the first and second counter stages and the toggle stage receive a same set signal and a same reset signal.

17. A method for interfacing with a driving stage connected to an electrical motor, the driving stage comprising a complementary pair of first and second power elements connected in an inverter configuration between first and second voltage references, the method comprising:

connecting a first counter stage to a first input terminal receiving a PWM input signal;

connecting a second counter stage to an output of the first counter stage;

connecting a toggle stage to the first input terminal and to an output of the second counter stage;

connecting an output of the toggle stage to a control terminal of the first power element; and

connecting the output of the first counter stage to a control terminal of the second power element for providing a delayed PWM output signal thereto; and

the toggle stage generating a second PWM output signal, the second PWM output signal being kept at a desired low level in correspondence with switching of the PWM input signal having a lower duration than a predetermined duration.

18. A method according to claim 17, wherein the first and second counter stages and the toggle stage are synchronized by a same clock signal.

19. A method according to claim 18, wherein the predetermined duration corresponds to 2N times a period of the clock signal.

20. A method according to claim 19, wherein the toggle stage comprises a state machine.

21. A method according to claim 20, wherein the state machine has the following sequence of operating states:

changing from a first inactive state to a second wait state based upon a low-high transition of the PWM input signal;

changing from the second wait state to a third low logic level state based upon a low-high transition of a delayed signal generated by the second counter stage and delayed by N times the clock period;

changing from the third low logic level state to a fourth transition state based upon a high-low transition of the PWM input signal;

changing from the fourth transition state back to the first inactive state based upon a high-low transition of the delayed signal; and

the second PWM output signal performing a low-high transition delayed by 2N times the clock period with respect to the high-low transition of the PWM input signal when the state machine goes back to the first inactive state.

22. A method according to claim 21, wherein the state machine further has the following sequence of operating states:

changing from the third low logic level state to the fourth transition state based upon a high-low transition of the PWM input signal preceding the high-low transition of the delayed signal;

changing from the fourth transition state to a fifth low logic level state based upon a low-high transition of the PWM input signal;

changing from the fifth low logic level state to the second wait state based upon a high-low transition of the delayed signal;

changing from the second wait state to the third low logic level state based upon a low-high transition of the delayed signal;

changing from the third low logic level state to the fourth transition state based upon a low level of the input signal;

changing from the fourth transition state back to the first inactive state based upon a high-low transition of the delayed signal; and

when the state machine changes back to the first inactive state, the second output signal performing a low-high transition delayed by 2N times the clock period with respect to the high-low transition of the PWM input signal, the second output signal being kept at a low level during the high-low-high transition of the input signal which is lower than the predetermined duration.

23. A method according to claim 22, wherein the state machine changes from the third low logic level state to the first inactivity state based upon a high-low transition of the delayed signal immediately following a low-high transition of the delayed signal.

24. A method according to claim 17, wherein the first and second counter stages and the toggle stage receive a same set signal and a same reset signal.