Startup circuit for converter with pre-biased load

• US 7,034,586 B2
• Filed: 06/10/2004
• Issued: 04/25/2006
• Est. Priority Date: 03/05/2004
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Day, Brandon D., Mehas, Gustavo J., Leith, James W.
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US10/865,373
• Publication Number:
  US 20050194951A1
• Time in Patent Office: 684 Days
• Field of Search: 327/143, 327/540, 327/541, 323/901
• US Class Current: 327/143
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: Y10S 323/901 Starting circuits

Abstract

A method of starting a DC—DC converter into a precharged output voltage including generating a reference voltage having a linear relationship with the output voltage such that the reference voltage ranges between a minimum and maximum voltage level of a PWM triangular waveform as the output voltage ranges between zero and an input voltage level, and enabling output switching of the DC—DC converter when the reference voltage is approximately equal to a compensation signal generated by an error amplifier comparing the reference voltage with a feedback signal representative of the output voltage. Generating a reference voltage may include applying a first current based on the input voltage through two resistors to develop the minimum and maximum voltage levels, applying the first current in one direction through a third resistor, and applying a second current based on the output voltage through the third resistor in the opposite direction.

Claims

1. A startup circuit for a DC—

DC power converter, the power converter including an error amplifier which provides a compensation signal to a pulse width modulation (PWM) circuit that uses the compensation signal and a triangular PWM waveform to develop a PWM signal to control a switching circuit which converts an input voltage to an output voltage relative to a common power reference voltage, the switching circuit including an enable input, said startup circuit comprising;

a first circuit that establishes a minimum peak voltage and a maximum peak voltage for the triangular PWM waveform;

a second circuit that establishes a reference voltage having a linear relationship with the output voltage, wherein said reference voltage ranges from said minimum to maximum peak voltages while the output voltage ranges from the common power reference voltage to the level of the input voltage; and

a comparator having a first input for receiving the compensation signal, a second input receiving said reference voltage, and an output providing an enable signal which is for providing to the enable input of the switching circuit.

2. The startup circuit of claim 1, wherein said second circuit comprises:

a bias circuit that provides a bias node;

a reference resistor having a first end coupled to said bias node and a second end coupled to a reference node that develops said reference voltage;

a first current generator that develops a first current proportional to the input voltage;

a second current generator that develops a second current proportional to the output voltage;

a first current mirror circuit, coupled to said first current generator, that applies said first current through said reference resistor from said bias node to said reference node; and

a second current mirror circuit, coupled to said second current generator, that applies said second current through said reference resistor from said reference node to said bias node;

wherein said first and second current generators and said reference resistor are configured such that said reference voltage is approximately equal to said minimum peak voltage if the output voltage is at the common power reference voltage and is approximately equal to said maximum peak voltage if the output voltage is at the level of the input voltage.

3. The startup circuit of claim 2, the DC—

DC power converter including an output inductor coupled between an output node that develops the output voltage and to an intermediate phase node of the switching circuit, wherein said second current generator senses the output voltage via the phase node.

4. The startup circuit of claim 2, further comprising:

a first resistor having approximately the same resistance as said reference resistor and having a first end coupled to said bias node and a second end;

a second resistor having approximately the same resistance as said reference resistor and having a first end coupled to said bias node and a second end; and

a third current mirror circuit, coupled to said first current generator, that applies said first current into said second end of said first resistor and that draws said first current from said second end of said second resistor;

wherein said second end of said first resistor develops said maximum peak voltage and said second end of said second resistor develops said minimum peak voltage.

5. The startup circuit of claim 4, wherein said second current generator is configured to generate said second current at twice the current level of said first current if the output voltage is approximately equal to the input voltage.

6. The startup circuit of claim 4, further comprising:

a first voltage divider for dividing the input voltage and providing an input sense voltage;

a second voltage divider for dividing the output voltage and providing an output sense voltage;

said first current generator comprising a first transconductance amplifier having an input receiving said input sense voltage and an output that generates said first current across a third resistor to maintain its voltage at approximately the same voltage level as said input sense voltage;

said second current generator comprising a second transconductance amplifier having an input receiving said output sense voltage and an output that generates said second current across a fourth resistor to maintain its voltage at approximately the same voltage level as said output sense voltage; and

wherein said third resistor has approximately twice the resistance of said fourth resistor.

7. The startup circuit of claim 1, wherein said second circuit comprises:

a first resistor having a first end for receiving the input voltage and a second end;

a second resistor having a first end for receiving the output voltage, a second end that develops said reference voltage, and a resistance approximately equal to said first resistor;

a first amplifier having an inverting input receiving said maximum peak voltage, a non-inverting input coupled to said second end of said first resistor and an output;

a buffer amplifier that maintains its output at said minimum peak voltage;

a first current device having a current path coupled between said second end of said first resistor and said output of said buffer amplifier and having a control input coupled to said output of said first amplifier; and

a second current device, configured substantially similar to said first current device, having a current path coupled between said second end of said second resistor and said output of said buffer amplifier and having a control input coupled to said output of said first amplifier;

wherein said first amplifier controls said first current device to maintain voltage at said second end of said first resistor approximately equal to said maximum peak voltage.

8. A DC—

DC converter, comprising;

an output switching circuit, having an enable input for receiving an enable signal, that, when enabled, switchably applies an input voltage to an output inductor to develop an output voltage based on a PWM signal;

an error amplifier that generates a compensation voltage based on an output voltage feedback signal compared with a reference voltage;

PWM logic that generates said PWM signal based on said compensation voltage and a ramp signal ranging between minimum and maximum ramp voltages; and

a startup circuit, comprising;

a reference circuit that generates said reference voltage to vary in a linear manner relative to said output voltage between said minimum ramp voltage if said output voltage is zero and said maximum ramp voltage if said output voltage is at the same voltage as said input voltage; and

a comparator that compares said compensation voltage with said reference voltage and that provides said enable signal.

9. The DC—

DC converter of claim 8, wherein said reference circuit comprises;

a bias circuit that provides a bias node;

a reference resistor having a first end coupled to said bias node and a second end coupled to a reference node that develops said reference voltage;

a first transconductance amplifier circuit that provides a first current based on said input voltage;

a second transconductance amplifier circuit that provides a second current based on said output voltage;

a first current mirror that asserts said first current through first and second resistors coupled to said bias circuit to develop said minimum and maximum ramp voltages;

a second current mirror that asserts said first current through said reference resistor in one direction; and

a third current mirror that asserts said second current through said reference resistor in the opposite direction.

10. The of claim 9, wherein said output voltage is sensed via said output inductor at startup.

11. The DC—

DC converter of claim 9, wherein said second transconductance amplifier circuit is configured to generate said second current at twice the current level of said first current when said output voltage is approximately equal to said input voltage.

12. The DC—

DC converter of claim 11, wherein said first transconductance amplifier circuit includes a first transconductance amplifier that maintains a voltage representative of said input voltage across a third resistor, wherein said second transconductance amplifier circuit includes a second transconductance amplifier that maintains a voltage representative of said output voltage across a fourth resistor, and wherein said third resistor is twice the resistance of said fourth resistor.

13. The DC—

DC converter of claim 9, wherein said startup circuit is implemented on an integrated circuit receiving a supply voltage and wherein said bias circuit divides said supply voltage to provide said bias node.

14. The DC—

DC converter of claim 8, wherein said reference circuit comprises;

a first resistor having a first end coupled to sense said input voltage and a second end;

a second resistor having a first end coupled to said output voltage, a second end that develops said reference voltage, and a resistance approximately equal to said first resistor;

a first amplifier having an inverting input receiving said maximum ramp voltage, a non-inverting input coupled to said second end of said first resistor and an output;

a buffer amplifier that maintains its output at said minimum ramp voltage;

a first transistor having a current path coupled between said second end of said first resistor and said output of said buffer amplifier and having a control input coupled to said output of said first amplifier; and

a second transistor, equivalent to said first transistor, having a current path coupled between said second end of said second resistor and said output of said buffer amplifier and having a control input coupled to said output of said first amplifier;

wherein said first amplifier controls said first transistor to maintain voltage at said second end of said first resistor approximately equal to said maximum ramp voltage.

15. The DC—

DC converter of claim 14, wherein said second resistor is coupled to sense said output voltage at a phase node coupled to said output inductor.

16. A method of starting a DC—

DC converter into a precharged output voltage, comprising;

generating a reference voltage having a linear relationship with the output voltage, wherein the reference voltage ranges between a minimum and maximum voltage level of a PWM triangular waveform as the output voltage ranges between zero and an input voltage level; and

enabling output switching of the DC—

DC converter when the reference voltage is approximately equal to a compensation signal generated by an error amplifier comparing the reference voltage with a feedback signal representative of the output voltage.

17. The method of claim 16, wherein said generating a reference voltage comprises:

applying a first current based on the input voltage through first and second resistors coupled together at a first node to develop the minimum and maximum voltage levels of the PWM triangular waveform;

applying the first current in one direction through a third resistor having a first end coupled to the first node and having a second end that develops the reference voltage; and

applying a second current based on the output voltage through the third resistor in the opposite direction.

18. The method of claim 16, wherein said generating a reference voltage comprises:

coupling a first resistor between the input voltage and a first node;

coupling a second, equal-valued resistor between the output voltage and a second node;

coupling the current path of a first transistor between the first node and a third node;

coupling the current path of a second transistor between the second node and the third node;

maintaining the voltage of the third node at the minimum voltage level of the PWM triangular waveform;

applying a control signal to the first transistor to maintain voltage of the first node at the maximum voltage level of the PWM triangular waveform, wherein the current path of the first transistor develops a first resistance; and

applying the control signal to the second transistor such that its current path maintains a resistance between the second and third nodes that is equivalent to the first resistance.