DCT/IDCT with minimum multiplication

• US 7,035,332 B2
• Filed: 08/07/2001
• Issued: 04/25/2006
• Est. Priority Date: 07/31/2001
• Status: Expired due to Fees

• Current Assignee: Micronas Gmbh (TDK Corporation)
• Original Assignee: WIS Technologies, Inc.
• Inventors: Sha, Li, Xiang, Shuhua, Zhu, Ping, Luo, Yaojun, He, Ouyang
• Primary Examiner(s): An, Shawn S.
• Application Number:
  US09/924,140
• Publication Number:
  US 20050207488A1
• Time in Patent Office: 1,722 Days
• Field of Search: 375/240.02, 375/240.18, 375/240.2, 375/240.25, 375/240.26, 375/240.01, 375/240.24, 708/400, 708/402, 708/401, 382/250, 382/233, 382/248, 382/235
• US Class Current: 375/240.02
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes two sets of lookup tables to provide multiplication and add operations for the DCT and IDCT functions. Another embodiment of a core include one set of lookup tables, while another embodiment of a core includes no lookup table. The DCT/IDCT module provides forward DCT and IDCT functionality without the use of additional multipliers.

Claims

1. A DCT/IDCT circuit for enabling forward and inverse discrete cosine transform of a data block, comprising:

a plurality of cores, each having input data and output data, wherein the input data includes external data and feedback data output from selected ones of the cores, and wherein the plurality of cores includes

a first core having a first input, a second input and an output for performing forward DCT and IDCT operations, the first input of the first core coupled to receive external data;

a second core having a first input, a second input and an output for performing forward DCT and IDCT operations, the first input of the second core coupled to receive external data, and the second input of the second core coupled to the output of the first core; and

a third core having a first input, a second input and an output for performing forward DCT and IDCT operations, the first input of the third core coupled to receive external data, the second input of the third core coupled to the output of the second core and the output of the third core coupled to the second input of the first core to provide feedback data.

2. The DCT/IDCT circuit according to claim 1, further comprising:

a sequence generator coupled to each core.

3. The DCT/IDCT circuit according to claim 1, wherein the selected ones of the cores comprises four cores.

4. The DCT/IDCT circuit according to claim 1, wherein the external data comprises the data block, the data block including prediction data processed by an MEC engine communicatively coupled to the DCT/IDCT circuit.

5. The DCT/IDCT circuit according to claim 1, wherein the external data comprises the data block, the data block including reconstruction data processed by an inverse quantizer module communicatively coupled to the DCT/IDCT circuit.

6. The DCT/IDCT circuit according to claim 1, wherein the plurality of cores comprises 8 cores.

7. The DCT/IDCT circuit according to claim 1, wherein the plurality of cores comprises four types of cores.

8. The DCT/IDCT circuit according to claim 7, wherein a first type of core includes a main register for storing the input data and the feedback data.

9. The DCT/IDCT circuit according to claim 7, wherein a second type of core includes a first pair of lookup tables, and a third type of core includes a second pair of lookup tables.

10. The DCT/IDCT circuit according to claim 7, wherein a fourth type of core includes two pairs of lookup tables.

11. A DCT circuit enabling forward discrete cosine transform of a data block, comprising:

a plurality of cores, each having input data and output data, wherein the input data includes external data and feedback data output from selected ones of the cores, and wherein the plurality of cores includes

a first core having a first input, a second input and an output for performing forward DCT operations, the first input of the first core coupled to receive external data, and

a second core having a first input, a second input and an output for performing forward DCT operations, the first input of the second core coupled to receive external data, the second input of the second core coupled to the output of the first core; and

a third core having a first input, a second input and an output for performing forward DCT operations, the first input of the third core coupled to receive external data, the second input of the third core coupled to the output of the second core and the output of the third core coupled to the second input of the first core to provide feedback data.

12. The DCT circuit according to claim 11, further comprising:

a sequence generator coupled to each core.

13. The DCT circuit according to claim 11, wherein the selected ones of the cores comprises four cores.

14. An IDCT circuit enabling inverse discrete cosine transform of a data block, comprising:

a plurality of cores, each having input data and output data, wherein the input data includes external data and feedback data output from selected ones of the cores, and wherein the plurality of cores includes

a first core having a first input, a second input and an output for performing IDCT operations, the first input of the first core coupled to receive external data, and

a second core having a first input, a second input and an output for performing IDCT operations, the first input of the second core coupled to receive external data, the second input of the second core coupled to the output of the first core; and

a third core having a first input, a second input and an output for performing IDCT operations, the first input of the third core coupled to receive external data, the second input of the third core coupled to the output of the second core and the output of the third core coupled to the second input of the first core to provide feedback data.

15. The IDCT circuit according to claim 14, further comprising:

a sequence generator coupled to each core.

16. The IDCT circuit according to claim 14, wherein the selected ones of the cores comprises four cores.

17. A DCT/IDCT circuit for enabling forward and inverse discrete cosine transform of a data block, comprising:

means for receiving input data associated with the data block;

coupled to the means for receiving, first means for selecting one of the input data and a sum of the input data and feedback data to provide first output data;

coupled to the first means, second means for determining a sum of first partial products based on the input data, the feedback data, and first coefficient data to provide second output data;

coupled to the means for receiving input data, third means for determining a sum of second partial products based on the input data, the feedback data, and second coefficient data to provide third output data;

coupled to the means for receiving input data, fourth means for determining a sum of additional partial products based on the input data, the feedback data, and additional coefficient data to provide third output data; and

means for outputting the first output data, the second output data and the third output data collectively representing a result of one of the forward discrete cosine transform and the inverse discrete cosine transform.

18. The DCT/IDCT circuit according to claim 17, further including means for obtaining the final result within two clock cycles.