Circuit testing with ring-connected test instrument modules

• US 7,035,755 B2
• Filed: 08/16/2002
• Issued: 04/25/2006
• Est. Priority Date: 08/17/2001
• Status: Expired due to Fees

• Current Assignee: Credence Systems Corporation (COHU Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: West, Burnell G., Cullen, Jamie S., Whyte, Robert, Zaman, Naveed, Jones, Michael F., Gazounaud, Yann, Fritzsche, William
• Primary Examiner(s): WACHSMAN, HAL D
• Application Number:
  US10/222,191
• Publication Number:
  US 20030105607A1
• Time in Patent Office: 1,348 Days
• Field of Search: 702/121, 702/108, 702117-120, 702/122, 702/123, 702/125, 702/178, 702186-188, 702/189, 700/306, 714/724, 714/736, 714/700, 714/701, 714/814, 714/815, 714/775, 714/712, 714/718, 714/717, 714/730, 714/731, 714/742, 714/743, 714/744, 324/73.1, 324/158.1, 370/241, 370/242, 709/208, 709/209, 709/251, 717/105
• US Class Current: 702/121
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence

Abstract

Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Claims

1. A system for controlling test instruments that are configured to test one or more integrated circuits, the system comprising:

a master clock directly connected to each of two or more test instruments, the master clock being configured to provide a master clock signal to the two or more test instruments, the two or more test instruments being connected to form a communication ring, each of the two or more test instruments including an input port and an output port, the output port of a first test instrument being connected only to the input port of a second test instrument, a data word provided to the input port of the first test instrument being provided to the input port of the second test instrument only by the output port of the first test instrument; and

a controller connected to the communication ring, the controller being configured to align counters of the two or more test instruments to derive a common clock time value from the master clock signal, the controller being further configured to generate and send data words into the communication ring to carry the data words to each of the two or more test instruments, the data words including at least one data word specifying a test event to be performed, a common clock time value, and at least one of the two or more test instruments, wherein the at least one of the two or more test instruments is configured to perform the test event at the time specified by the common clock time value.

2. The system of claim 1, wherein:

at least one of the two or more test instruments can delay a data word carried by the communication ring without coordinating the delay with any other test instrument.

3. The system of claim 2, wherein:

at least one of the two or more test instruments can replace a bus word carried in the communication ring with a delayed bus word.

4. The system of claim 1, further comprising:

an adaptor for converting one of the two or more test instruments into a module, the adaptor including a processor, memory, and a data bus that is configured for connecting the processor and memory to the communication ring and, furthermore, for exchanging data with one or more of the two or more test instruments.

5. The system of claim 4, wherein the one test instrument of the two or more test instruments converted into a module comprises an off-the-shelf test instrument.

6. The system of claim 1, wherein:

at least one of the two or more test instruments is constructed as a module.

7. The system of claim 1, further comprising:

a first adaptor and a second adaptor, each adaptor for converting the first and second test instruments into modules, the first adaptor including a processor and logic to insert a partial sync word into the communication ring, the second adaptor including a processor and logic to add synchronization information to the partial sync word and to return the partial sync word to the first adaptor.

8. The system of claim 7, wherein the synchronization information added to the partial sync word includes a state history of the second test instrument.

9. The system of claim 1, wherein the controller is configured to insert control data words into the communication ring, the control data words carrying test function information to a test instrument of the two or more test instruments.

10. The system of claim 1, wherein the controller is configured to insert a read data word into the communication ring, the read data word requesting measured test data from a test instrument.

11. The system of claim 1, wherein the communication ring carries bus words in a daisy chain fashion from the output port of each of the two or more test instruments to the input port of an adjacent test instrument.

12. The system of claim 1, wherein the data words include an address specifying at least one target test instrument.

13. The system of claim 1, wherein the controller is configured to insert bus words into the communication ring through a test head interface.

14. The system of claim 1, wherein the controller is configured to insert data words that include information for testing a second integrated circuit into the communication ring, the inserting occurring during a testing of a first integrated circuit.

15. The system of claim 1, further comprising:

status monitoring devices for receiving reports from each of the two or more test instruments, a report of a test instrument specifying the status and capability of the test instrument.

16. The system of claim 15, further comprising:

a status monitoring link separate from the communication ring.

17. The system of claim 15, wherein:

the reports comprise data words exchanged between the controller and the two or more test instruments over the communication ring.

18. The system of claim 1, wherein:

the first test instrument comprises a first processor and logic configured to insert into the communication ring a data word that comprises information describing a first test event, and

the second test instrument comprises a second processor and logic configured to add to the data word information describing a second test event.

19. The system of claim 18, wherein:

the information describing the first test event comprises information acquired by the first test instrument; and

the information describing the second test event comprises information acquired by the second test instrument.

20. The system of claim 19, wherein:

the controller processes the data word.

21. The system of claim 19, wherein:

at least one of the two or more test instruments processes the data word.

22. The system of claim 18, wherein:

the data word comprises information that specify a common clock time value and a test event that occurred at the common clock time value.

23. A data and control signal distribution subsystem for an automatic circuit test system having test instruments for performing tests on a electrical circuit, the subsystem comprising:

a communication ring for coupling test instruments in the system to each other in a daisy chain fashion, where the communication ring is configured to connect to each test instrument through a single input port and a single output port;

a master clock circuit providing a master clock signal; and

a dedicated clock signal path between each test instrument in the test system and the master clock circuit, the dedicated clock signal paths together distributing the master clock signal to all test instruments in parallel;

wherein the communication ring is the exclusive path for test instruments in the test system to send synchronization signals and command signals to one another during a performance of a test, and the master clock signal received through a dedicated signal path is the exclusive global clock signal provided to test instruments in the test system.

24. The subsystem of claim 23, further comprising:

an adaptor for converting one of the test instruments into a module, the adaptor including a processor, memory, and a data bus that is configured for connecting the processor and memory to the communication ring and, furthermore, for exchanging data with one or more of the test instruments.

25. The subsystem of claim 23, further comprising:

a first adaptor for converting a first test instrument into a module, the first adaptor including a processor and logic to insert a partial sync word into the communication ring; and

a second adaptor for converting a second test instrument into a module, the second adaptor including a processor and logic to add synchronization information to the partial sync word and to return the partial sync word to the first adaptor.

26. The subsystem of claim 23, further comprising:

status monitoring devices for receiving reports from each of the test instruments, a report of a test instrument specifying the status and capability of the test instrument.

27. A computer program product, tangibly stored on machine-readable medium, for controlling one or more test instrument modules that are configured to test one or more integrated circuits in accordance with a test process, the product comprising instructions to cause a test system to:

identify a first test instrument module of the one or more test instrument modules that are configured to test integrated circuits in accordance with a test process, a test instrument module being a test instrument implemented as a module and including testing circuitry;

identify an independent test thread for the first test instrument module, the test thread comprising instructions for generating data words to be sent to another of the test instrument modules; and

send the test thread to the first test instrument module.

28. The computer program product of claim 27, further comprising instructions to:

align counters of the one or more test instrument modules to a common clock cycle.

29. The computer program product of claim 28, further comprising instructions to:

generate a data word that specifies, a test event, a particular common clock cycle, and one or more of the test instrument modules to perform the specified test event at the common clock cycle.

30. A method for controlling and synchronizing one or more test instruments connected in a communication ring to test an electrical circuit, the method comprising:

setting and maintaining synchronization of an internal time register of each of the one or more test instruments to a common clock cycle by using a global clock signal of a master clock, the common clock cycle providing common clock time values for scheduling test events;

inserting bus words into the communication ring to carry the bus words to each of the one or more test instruments, the inserted bus words including at least one bus word specifying a scheduled common clock time value for performing a test event by a target test instrument; and

reading, by the target test instrument, the at least one bus word and using the scheduled common clock time value and the common clock cycle in the internal time register of the target test instrument to determine when to perform the test event.

31. The method of claim 30, further comprising:

inserting into the communication ring a partial sync word that describes a first aspect of a particular test event, the first aspect being monitored by a first test instrument; and

adding to the partial sync word information that describes a second aspect of the particular test event, the second aspect being monitored by a second test instrument.

32. The method of claim 31, further comprising:

processing the partial sync word to determine whether the particular test event has been completed.

33. A system for controlling two or more test instruments that are configured to test one or more integrated circuits, the system comprising:

a master clock connected to each of the two or more test instruments, the master clock being configured to provide, through a parallel and dedicated clock signal path, a master clock signal to each of the two or more test instruments; and

a controller connected to a communication ring formed by connecting together the two or more test instruments, each of which includes an input port and an output port, the output port of a test instrument in the communication ring being connected only to the input port of a succeeding test instrument in the communication ring, the input port of the test instrument being connected only to the output port of a preceding test instrument in the communication ring, wherein data words are propagated through the communication ring such that a data word provided to the input port of the test instrument is provided to the input port of the succeeding test instrument only through the output port of the test instrument, and wherein the controller is configured to synchronize counters of the two or more test instruments to derive a common clock time value from the master clock signal, the controller being able to synchronize counters of the two or more test instruments when a data word is inserted into the communication ring during synchronization.