Automated processor generation system for designing a configurable processor and method for the same

• US 7,036,106 B1
• Filed: 02/17/2000
• Issued: 04/25/2006
• Est. Priority Date: 02/17/2000
• Status: Expired due to Term

• Current Assignee: Tensilica Incorporated
• Original Assignee: Tensilica Incorporated
• Inventors: Killian, Earl A., Wang, Albert Ren-Rui, Goodwin, David William, Gonzalez, Ricardo E., Parameswar, Akilesh, Konas, Pavlos, Srinivasan, Rangarajan, Bhattacharyya, Nupur, Medina, Marines Puig, Lichtenstein, Walter David, Songer, Christopher Mark, Ruddell, Richard, Maydan, Dror E.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US09/506,502
• Time in Patent Office: 2,259 Days
• Field of Search: 715/15, 716/2, 716/17, 716/18, 716/1, 713/324, 703/15
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Claims

1. A system for designing a configurable processor, the system comprising:

hardware generation means for, based on a configuration specification including a predetermined portion and a user-defined portion, generating a description of a hardware implementation of the processor, the predetermined portion specifying a configuration of a core register file, and the user-defined portion specifying whether to include a user-defined register file supporting a freely user-defined data type in the processor in addition to the core register file; and

software generation means for, based on the configuration specification, generating software development tools specific to the hardware implementation;

wherein the hardware generation means includes register generation means for, based on the user-defined portion of the configuration specification, generating a description of the user-defined register file separate from and in addition to a description of the core register file in the description of the hardware implementation of the processor; and

the software generation means is for, based on the user-defined portion, including software related to the user-defined processor register file in the software development tools.

2. The system of claim 1, wherein the software related to the user-defined processor register file includes an instruction for accessing elements in the register file according to a field of the instruction.

3. The system of claim 2, wherein the hardware generation means is for generating at least part of the description of the hardware implementation in a register transfer level hardware description language.

4. The system of claim 1, wherein the configuration specification defines the user-defined register file using a statement specifying the width of elements in the user-defined register file.

5. The system of claim 1, wherein the configuration specification defines the user-defined register file using a statement specifying the number of elements in the user-defined register file.

6. The system of claim 1, wherein the hardware generation means is for determining a number of at least one of read ports and write ports of the user-defined register file independently of the configuration specification.

7. The system of claim 1, wherein the hardware generation means is for generating, as part of the processor hardware implementation description, a description of logic to assign write ports of the user-defined register file to instruction operands to minimize data staging costs.

8. The system of claim 1, wherein the hardware generation means is for generating pipeline logic for accessing the user-defined register file.

9. The system of claim 8, wherein read ports for the user-defined register file are read in the earliest stage of any instruction that uses them as a source operand.

10. The system of claim 8, wherein write ports for the user-defined register file are read in the latest stage of any instruction that uses it as a destination operand or in an instruction commit stage if later.

11. The system of claim 1, wherein the hardware generation means is for generating, as part of the hardware implementation of the processor, logic to provide a read port for the user-defined register file for each field, within an instruction accessing the user-defined register file, used to select a source operand from the user-defined register file.

12. The system of claim 1, wherein the hardware generation means is for generating, as part of the hardware implementation of the processor, bypass logic for accessing the user-defined register file.

13. The system of claim 12, wherein the hardware generation means is for generating the interlock logic for a given pipeline of the processor described by the configuration specification based on instruction operand and state usage descriptions in the configuration specification.

14. The system of claim 1, wherein the hardware generation means is for generating, as part of the hardware implementation of the processor, interlock logic for accessing the register file.

15. The system of claim 14, wherein the hardware generation means is for generating the interlock logic based on scheduling information in the configuration specification.

16. The system of claim 14, wherein the hardware generation means is for generating the interlock logic for a given pipeline of the processor described by the configuration specification based on instruction operand and state usage descriptions in the configuration specification.

17. The system of claim 1, wherein the hardware generation means is for generating the processor hardware implementation description to use at least one portion of processor logic described by the predetermined portion of the configuration specification to support access of the user-defined register file.

18. The system of claim 17, wherein the at least one portion of processor logic includes address computation logic.

19. The system of claim 18, wherein the address computation logic includes address adder logic.

20. The system of claim 18 wherein the at least one portion of processor logic includes data aliment logic shared between the portions of the processor corresponding to predetermined and user-defined portions of the configuration specification.

21. The system of claim 18 wherein the at least one portion of processor logic is a data memory.

22. The system of claim 1, wherein the user-defined portion of the configuration specification includes a description of an instruction which conditionally writes to the user-defined register file.

23. The system of claim 1, wherein the software generation means is for generating, as part of the software relating to the user-defined register file, diagnostic tests for design verification and manufacturing of the processor based on the configuration specification.

24. The system of claim 1, wherein:

the configuration specification includes both reference and implementation semantics for instructions of the processor; and

the reference semantics can be used to verify design correctness of the implementation semantics.

25. The system of claim 1, wherein:

the processor instruction set description language includes instruction test cases; and

the software generation means is for generating diagnostics for the test cases.

26. The system of claim 1, wherein the software generation means is for automatically generating test vectors by sampling operands to instructions in the processor instruction set description language while running an application.

27. The system of claim 1, wherein the software generation means is for generating at least a portion of an operating system as part of the software relating to user-defined states and register files.

28. The system of claim 27, wherein the generated portion of the operating system includes save and restore sequences for processor state.

29. The system of claim 28, wherein the save and restore sequences are generated with respect to interdependencies of component states and is valid for those interdependencies.

30. The system of claim 27, wherein the operating system is capable of saving less than an entirety of processor state in accordance with a dynamic reference by a new task after switching contexts.

31. The system of claim 27, wherein:

the user-defined portion of the configuration specification defines a software data type not found in the predetermined portion of the configuration specification; and

the compiler supports the software data type.

32. The system of claim 1, wherein the software generation means is for generating at least one of a compiler, a linker, a simulator and a debugger as part of the software relating to the user-defined register file.

33. The system of claim 1, wherein:

the software generation means is for generating a compiler as part of the software relating to the user-defined register file; and

the compiler is capable of allocating program variables to registers in the user-defined register file.

34. The system of claim 33, wherein the compiler is further capable of loading a value from memory into a register in the user-defined register file, and storing a value in a register of the user-defined register file into memory.

35. The system of claim 33, wherein the compiler is further capable of moving a value from one register in a user-defined register file to another register in a user-defined register file.

36. The system of claim 33, wherein the compiler is for using scheduling information in the configuration specification to determine stall cycles of instructions in the software generated by the software generation means which access the user-defined register file.

37. The system of claim 1, wherein the software generation means is for automatically generating a monitor to check for coverage of bypass paths.

38. The system of claim 1, wherein the user-defined portion of the configuration specification supports one or more user-defined instructions that are added to a predefined instruction set of the processor.