Method for producing a wafer interposer for use in a wafer interposer assembly

• US 7,036,218 B2
• Filed: 02/24/2003
• Issued: 05/02/2006
• Est. Priority Date: 12/15/2000
• Status: Expired due to Fees

• Current Assignee: Transpacific Multicast, LLC
• Original Assignee: Eaglestone Partners I LLC
• Inventors: Pierce, John L.
• Primary Examiner(s): Tugbang, A. Dexter
• Assistant Examiner(s): PHAN, THIEM D
• Application Number:
  US10/373,414
• Publication Number:
  US 20030128044A1
• Time in Patent Office: 1,163 Days
• Field of Search: 298/42, 295/93, 298/29, 298/44, 298/47, 298/50, 298/32, 298/40, 257/668, 257/690, 324/158.1, 324/754, 324/755, 324/765, 324/761, 439/67, 361/777, 438/637
• US Class Current: 29/842
• CPC Class Codes: G01R 1/0433 Sockets for IC's or transistors
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 Monolayer substrate
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base
• CPC Class Codes: Y10T 29/49151 by deforming or shaping
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths
• CPC Class Codes: Y10T 29/49162 by using wire as conductive path

Abstract

A method for producing a wafer interposer (210) for use in a wafer interposer assembly is disclosed. The wafer interposer (210) is produced by attaching solder bumps (140) to a lower surface of a support (120). First electrical terminals (130) are attached to an upper surface of the support (120) and substantially correspond to the solder bumps (140). First electrical pathways are provided that passes through the support (120) and connect the solder bumps (140) to the first electrical terminals (130). Second electrical terminals (310) are attached to the upper surface of the support (120). Second electrical pathways (320) connect the first electrical terminals (130) to the second electrical terminals (310).

Claims

1. A method of producing a wafer testing interposer comprising the steps of:

providing a support having a first surface and a second surface;

attaching first electrical terminals to the first surface in the form of a pattern;

coupling second electrical terminals to the second surface of the support such that the second electrical terminals substantially correspond to the first electrical terminals;

creating first electrical pathways passing through the support that connect the second electrical terminals to the first electrical terminals;

positioning third electrical terminals on the first surface of the support, the third electrical terminals positioned within the pattern of the first electrical terminals, the third electrical terminals having a greater size and pitch than the first electrical terminals; and

creating second electrical pathways that connect the first electrical terminals to the third electrical terminals.

2. The method as recited in claim 1 further comprising the step of arranging the first and second electrical terminals in a pattern distributed around the outer edges of the support.

3. The method as recited in claim 2 further comprising the step of arranging the first and second electrical terminals in a quadrilateral pattern distributed around the outer edges of the support.

4. The method as recited in claim 1 further comprising the step of attaching a semiconductor wafer having a plurality of semiconductor die to the support such that electrical terminals on the semiconductor die are electrically coupled to the second electrical tenninals, thereby forming a wafer interposer assembly.

5. The method as recited in claim 4 further comprising the step of testing the semiconductor die using the third electrical terminals.

6. The method as recited in claim 5 further comprising the step of performing parametric testing of the semiconductor die.

7. The method as recited in claim 5 further comprising the step of performing burn-in testing of the semiconductor die.

8. The method as recited in claim 5 further comprising the steps of grading a performance level of the semiconductor die.

9. The method as recited in claim 4 further comprising the step of integrating a portion of the wafer interposer assembly into a semiconductor package.

10. The method as recited in claim 9 wherein the step of integrating a portion of the wafer interposer assembly into a semiconductor package further comprises forming a semiconductor package selected from the group consisting of ball grid arrays, lan grid arrays, dual in-line packages and chip scale packages.

11. The method as recited in claim 9 wherein the step of integrating a portion of the wafer interposer assembly into a semiconductor package further comprises wire bonding the portion of the wafer interposer to form the semiconductor package.

12. The method as recited in claim 9 wherein the step of integrating a portion of the wafer interposer assembly into a semiconductor package further comprises flip chip connecting the portion of the wafer interposer to form the semiconductor package.

13. A method of producing a wafer testing interposer comprising the steps of:

providing a support having a first surface and a second surface;

attaching first electrical terminals to the first surface in the form of a pattern distributed around the outer edges of the support;

coupling second electrical terminals to the second surface of the support, each of the second electrical terminals corresponding to one of the first electrical terminals;

creating first electrical pathways passing through the support that connect the second electrical terminals to the corresponding first electrical terminals;

positioning third electrical terminals on the first surface of the support, the third electrical terminals positioned within the pattern of the first electrical terminals, the third electrical terminals having a greater size and pitch than the first electrical terminals, each of the third electrical terminals corresponding to one of the first electrical terminals; and

creating second electrical pathways that connect the third electrical terminals to the corresponding first electrical terminals.

14. The method as recited in claim 13 further comprising the step of attaching a semiconductor wafer having a plurality of semiconductor die to the support such that electrical terminals on the semiconductor die are electrically coupled to the second electrical terminals, thereby forming a wafer interposer assembly.

15. The method as recited in claim 14 further comprising the step of testing the semiconductor die using the third electrical terminals.

16. The method as recited in claim 15 further comprising the step of performing parametric testing of the semiconductor die.

17. The method as recited in claim 15 further comprising the step of performing burn-in testing of the semiconductor die.

18. The method as recited in claim 15 further comprising the steps of grading a performance level of the semiconductor die.

19. The method as recited in claim 14 further comprising the step of integrating a portion of the wafer interposer assembly into a semiconductor package.

20. The method as recited in claim 19 wherein the step of integrating a portion of the wafer interposer assembly into a semiconductor package further comprises forming a semiconductor package selected from the group consisting of ball grid arrays, lan grid arrays, dual in-line packages and chip scale packages.

21. The method as recited in claim 19 wherein the step of integrating a portion of the wafer interposer assembly into a semiconductor package further comprises wire bonding the portion of the wafer interposer to form the semiconductor package.

22. The method as recited in claim 19 wherein the step of integrating a portion of the wafer interposer assembly into a semiconductor package further comprises flip chip connecting the portion of the wafer interposer to form the semiconductor package.