Capacitive micromachined ultrasound transducer fabricated with epitaxial silicon membrane

• US 7,037,746 B1
• Filed: 12/27/2004
• Issued: 05/02/2006
• Est. Priority Date: 12/27/2004
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Mills, David Martin, Tian, Wei-Cheng, Smith, Lowell Scott, Fortin, Jeffrey Bernard, Logan, John Robert
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US11/023,252
• Time in Patent Office: 491 Days
• Field of Search: 438 48- 99, 438510-569
• US Class Current: 438/53
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type

Abstract

A capacitive micromachined ultrasound transducer (cMUT) cell is presented. The cMUT cell includes a lower electrode. Furthermore, the cMUT cell includes a diaphragm disposed adjacent to the lower electrode such that a gap having a first gap width is formed between the diaphragm and the lower electrode, wherein the diaphragm comprises one of a first epitaxial layer or a first polysilicon layer. In addition, a stress reducing material is disposed in the first epitaxial layer.

Claims

1. A method for fabricating a capacitive micromachined ultrasound transducer cell, the method comprising:

forming a cavity on a topside of a first substrate, wherein the cavity is defined by a plurality of support posts;

disposing a diaphragm on the plurality of support posts to form a composite structure with a top portion having a gap between the lower electrode and the diaphragm, wherein the diaphragm comprises one of a first epitaxial layer or a first polysilicon layer wherein the top portion comprises disposing one of the epitaxial layer or the first polysilicon layer on a second substrate, wherein one of the epitaxial layer or the polysilicon layer and the second substrate are oppositely doped and wherein a doping level in the first epitaxial layer is different than a doping level in the substrate; and

disposing a stress reducing material comprises geranium in one of the first epitaxial layer or the first polysilicon layer.

2. The method of claim 1, further comprising fabricating a bottom portion that comprises a lower electrode.

3. The method of claim 2, wherein fabricating the bottom portion comprises disposing a first oxide layer on a first side of a first substrate.

4. The method of claim 3, wherein fabricating the bottom portion comprises forming a cavity by etching the first oxide layer to form the cavity defined by a plurality of support posts.

5. The method of claim 4, further comprising disposing a second oxide layer on the first substrate within the cavity.

6. The method of claim 2, wherein the first substrate comprises the lower electrode.

7. The method of claim 1, wherein disposing the stress reducing material comprises implanting the stress reducing material in one of the first epitaxial layer or the first polysilicon layer.

8. The method of claim 1, wherein one of the first epitaxial layer or the first polysilicon layer comprises an n-type material and the second substrate comprises a p-type material.

9. The method of claim 1, wherein one of the first epitaxial layer or the first polysilicon layer comprises a p-type material and the second substrate comprises an n-type material.