Phase changeable memory devices having multi-level data storage elements and methods of fabricating the same

• US 7,037,762 B2
• Filed: 05/07/2003
• Issued: 05/02/2006
• Est. Priority Date: 05/10/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Horii, Hideki, Joo, Jae-Hyun
• Primary Examiner(s): Vu, David
• Application Number:
  US10/430,980
• Publication Number:
  US 20030222292A1
• Time in Patent Office: 1,091 Days
• Field of Search: 257/74, 257/208, 257/209, 257/211, 257528-530, 257/390, 257/758, 438/95, 438/128, 438131-132, 438/141, 438/380, 438/600, 365/51, 365/96
• US Class Current: 438/128
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A phase changeable memory device includes a lower interlayer dielectric layer on a semiconductor substrate. A plurality of first phase changeable data storage elements is disposed on the lower interlayer dielectric layer. A middle interlayer dielectric layer covers the first phase changeable data storage elements and the lower interlayer dielectric layer. A plurality of second phase changeable data storage elements is disposed on the middle interlayer dielectric layer. The first and second phase changeable data storage elements are arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns. A plate electrode overlies the first and second phase changeable data storage elements and is electrically connected to the first and second phase changeable data storage elements. Related fabrication methods are also disclosed.

Claims

1. A memory device comprising:

a lower interlayer dielectric layer on a semiconductor substrate;

a plurality of first phase changeable data storage elements on the lower interlayer dielectric layer;

a middle interlayer dielectric layer covering the first phase changeable data storage elements and the lower interlayer dielectric layer;

a plurality of second phase changeable data storage elements on the middle interlayer dielectric layer, the first and second phase changeable data storage elements being arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns; and

a plate electrode overlying the first and second phase changeable data storage elements and electrically connected to the first and second phase changeable data storage elements.

2. The memory device of claim 1, further comprising:

a plurality of first contact plugs passing through the lower interlayer dielectric layer; and

a plurality of second contact plugs passing through the middle interlayer dielectric layer and contacting the second phase changeable data storage elements, wherein the first contact plugs include a first group of first contact plugs that are in contact with the first phase changeable data storage elements and a second group of first contact plugs that are in contact with the second contact plugs.

3. The memory device of claim 2, wherein the first and second groups of first contact plugs are parts of the same material layer.

4. The memory device of claim 2, wherein the first contact plugs comprise at least one of TiN, TiAlN, TiSiN, TaAlN and TaSiN.

5. The memory device of claim 2, wherein the second contact plugs comprise at least one of titanium nitride (TiN), TiAlN, TiSiN, TaAlN and TaSiN.

6. The memory device of claim 1, further comprising:

a plurality of first contact plugs passing through the lower interlayer dielectric layer and contacting the first phase changeable data storage elements; and

a plurality of second contact plugs passing through the middle interlayer dielectric layer and contacting the second phase changeable data storage elements.

7. The memory device of claim 6, wherein the first contact plugs are part of the same material layer.

8. The memory device of claim 6, wherein the first contact plugs comprise at least one of TiN, TiAlN, TiSiN, TaAlN and TaSiN.

9. The memory device of claim 6, wherein the second contact plugs comprise a material having a different resistivity from the first contact plugs.

10. The memory device of claim 1, wherein the lower interlayer dielectric layer comprises a first insulating layer and a first chemical mechanical polishing (CMP) stopper layer on the first insulating layer.

11. The memory device of claim 10, wherein the first CMLP stopper layer comprises a silicon nitride layer.

12. The memory device of claim 1, wherein the middle interlayer dielectric layer comprises a second insulating layer and a second CMP stopper layer on the second insulating layer.

13. The memory device of claim 12, wherein the second CMP stopper layer comprises a silicon nitride layer.

14. The memory device of claim 1, wherein each of the first phase changeable data storage elements comprises a first phase changeable material layer pattern and a first top electrode on the first phase changeable material layer and wherein each of the second phase changeable data storage elements comprises a second phase changeable material layer pattern and a second top electrode on the second phase changeable material layer.

15. The memory device of claim 14, wherein the first and second phase changeable material layer patterns comprise a compound material comprising germanium (Ge), tellurium (Te) and stibium (Sb).

16. The memory device of claim 14, wherein the first and second top electrodes each comprise a titanium nitride (TiN) layer.

17. The memory device of claim 1, further comprising an upper interlayer dielectric layer interposed between the plate electrode and the second phase changeable data storage elements, wherein the plate electrode is electrically connected to the first phase changeable data storage elements through first metal contact holes that penetrate the upper interlayer dielectric layer and the middle interlayer dielectric layer, and wherein the plate electrode is electrically connected to the second phase changeable data storage elements through second metal contact holes that penetrate the upper interlayer dielectric layer.

18. A method of fabricating a phase changeable memory device comprising:

forming a lower interlayer dielectric layer on a semiconductor substrate;

forming a plurality of first phase changeable data storage elements on the lower interlayer dielectric layer;

forming a middle interlayer dielectric layer covering the first phase changeable data storage elements and the lower interlayer dielectric layer;

forming a plurality of second phase changeable data storage elements on the middle interlayer dielectric layer, the first and second phase changeable data storage elements being arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns; and

forming a plate electrode overlying the first and second phase changeable data storage elements and electrically connected to the first and second phase changeable data storage elements.

19. The method of claim 18, wherein the lower interlayer dielectric layer is formed by sequentially stacking a first insulating layer and a first CMP stopper layer.

20. The method of claim 19, wherein the first CMP stopper layer comprises a silicon nitride layer.

21. The method of claim 18, further comprising:

forming a plurality of first contact plugs passing through the lower interlayer dielectric layer prior to forming the first phase changeable data storage elements; and

forming a plurality of second contact plugs passing through the middle interlayer dielectric layer prior to forming the second phase changeable data storage elements, the first contact plugs comprising a first group of first contact plugs in contact with the first phase changeable data storage elements and a second group of first contact plugs under the second phase changeable data storage elements, and the second contact plugs being interposed between the second phase changeable data storage elements and the second group of first contact plugs.

22. The method of claim 21, wherein the first contact plugs comprise at least one of TiN, TiAIN, TiSiN, TaAIN and TaSiN.

23. The method of claim 21, wherein the second contact plugs comprise at least one of TiN, TiAlN, TiSiN, TaAlN and TaSiN.

24. The method of claim 18, wherein the middle interlayer dielectric layer is formed by sequentially stacking a second insulating layer and a second CMP stopper layer.

25. The method of claim 24, wherein the second CMP stopper layer comprise a silicon nitride layer.

26. The method of claim 18, wherein forming the first phase changeable data storage elements comprises:

sequentially forming a first phase changeable material layer and a first conductive layer on the lower interlayer dielectric layer; and

successively patterning the first conductive layer and the first phase changeable material layer to form first phase changeable material layer patterns two dimensionally arrayed on the lower interlayer dielectric layer and first top electrodes stacked on the first phase changeable material layer patterns.

27. The method of claim 26, wherein the first phase changeable material layer comprises a compound layer comprising germanium (Ge), tellurium (Te) and stibium (Sb), and wherein the first conductive layer comprises a titanium nitride (TiN) layer.

28. The method of claim 18, wherein forming the second phase changeable data storage elements comprises:

sequentially forming a second phase changeable material layer and a second conductive layer on the middle interlayer dielectric layer; and

successively patterning the second conductive layer and the second phase changeable material layer to form second phase changeable material layer patterns two dimensionally arrayed on the middle interlayer dielectric layer and second top electrodes stacked on the second phase changeable material layer patterns.

29. The method of claim 28, wherein the second phase changeable material layer comprises a compound layer comprising germanium (Ge), tellurium (Te) and stibium (Sb), and wherein the second conductive layer comprises a titanium nitride (TiN) layer.

30. The method of claim 18, further comprising:

forming a plurality of first contact plugs passing through the lower interlayer dielectric layer prior to forming the first phase changeable data storage elements; and

forming a plurality of second contact plugs passing through the middle interlayer dielectric layer and the lower interlayer dielectric layer prior to forming the second phase changeable data storage elements, the first contact plugs being in contact with the first phase changeable data storage elements and the second contact plugs being in contact with the second phase changeable data storage elements.

31. The method of claim 30, wherein the first contact plugs comprise at least one of TiN, TiAlN, TiSiN, TaAIN and TaSiN.

32. The method of claim 30, wherein the second contact plugs comprise a material having a different resistivity from the first contact plugs, and wherein the material layer comprises one of TiN, TiAlN, TiSiN, TaAlN and TaSiN.

33. The method of claim 18, wherein forming the plate electrode compnses:

forming an upper interlayer dielectric layer on the substrate having the second phase changeable data storage elements thereon;

patterning the upper interlayer dielectric layer and the middle interlayer dielectric layer to form metal contact holes that expose the first and second phase changeable data storage elements; and

forming a conductive layer pattern on the upper interlayer dielectric layer, the conductive layer pattern being electrically connected to the first and second phase changeable data storage elements through the metal contact holes.