Manufacturing method of semiconductor device

• US 7,037,788 B2
• Filed: 02/26/2004
• Issued: 05/02/2006
• Est. Priority Date: 05/30/2000
• Status: Expired due to Fees

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Ito, Hiroyasu, Kato, Masatoshi, Arakawa, Takafumi
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US10/786,107
• Publication Number:
  US 20040166637A1
• Time in Patent Office: 796 Days
• Field of Search: 438/268, 438/270, 438/272, 438/309
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

By improving profile of impurity concentration in a channel portion of an FET or an IGBT of a trench gate type, variation of threshold value is lessened, and a destruction caused by current concentration is prevented while suppressing deterioration of cut-off characteristics. An island of a base region of p-type is formed in a semiconductor substrate of n-type by carrying out high acceleration ion implantation twice followed by annealing, so that the impurity concentration profile in a channel portion changes gradually in a depth direction. Accordingly, it is possible to lessen variation of the threshold value and to reduce pinch resistance while at the same time improving sub-threshold voltage coefficient and conductance characteristics.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a second conductivity type region in a semiconductor substrate having a principal surface of a first conductivity type by implanting impurities of a second conductivity type two or more times;

forming a first conductivity type region inside the island of said second conductivity type region, said first conductivity type region having a higher impurity concentration than said semiconductor substrate;

forming a trench in a depth direction of said semiconductor substrate by anisotropic etching;

forming a sacrificed oxide film on an inner wall surface of the trench by thermal oxidation;

removing said sacrificed oxide film;

forming an insulation film in an interior of said trench;

filling said trench formed said insulation film with a polycrystalline silicon film;

forming a plurality of electric field alleviating regions by introducing impurities of the second conductivity type in a strip-wise shape so as to enclose a peripheral portion of said second conductivity type region;

forming a plurality of strip-wise highly doped second conductivity type regions each formed inside each of the electric field alleviating regions;

forming a plurality of strip-wise third trenches each formed inside each of the strip-wise second conductivity type regions in a depth direction of said semiconductor substrate by anisotropic etching;

forming a plurality of deeper second conductivity type regions each formed inside each of said third trenches by introducing impurities of the second conductivity type by two or more ion implantation steps;

forming a metal electrode which electrically connects each of said strip-wise second conductivity type region to each of said deeper second conductivity type region; and

forming a protection film at least on a surface of the semiconductor substrate except a region where said second conductivity type region underlies.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising, after the trench is filled with the polycrystalline silicon film:

patterning said film of polycrystalline silicon film so that the patterned polycrystalline silicon film has a T-shaped cross section with a wider width than an opening of said trench;

forming a highly doped first conductivity type region having a higher concentration than said first conductivity type region inside said first conductivity type region at a portion not coated by said polycrystalline silicon film; and

forming a highly doped second conductivity type layer region inside said first conductivity type region formed at a region enclosed by two of said trenches.

3. The method of manufacturing a semiconductor device according to claim 1, wherein, said second conductivity type region is formed by performing ion implantation two or more times, and the each ion implantation of the impurities of the second conductivity type is carried out under a condition that acceleration energy is 200 keV or higher.

4. The method of manufacturing a semiconductor device according to claim 2, wherein said highly doped first conductivity type region is formed under a condition that a dose of implant ions is 1.0×

10¹⁵ (atoms/cm²) or less.

10. The method of manufacturing a semiconductor device according to claim 1, wherein each of said deeper second-conductivity type region has a junction deeper than a junction of said second conductivity type region for forming a channel in a gate driving type power element having a high voltage withstanding characteristics.

5. A method of manufacturing a semiconductor device comprising:

forming a second conductivity type region in a semiconductor substrate having a principal surface of a first conductivity type;

forming a first conductivity type region inside said second conductivity type region, the first conductivity type region having a higher concentration than said semiconductor substrate;

forming a plurality of first trenches in a depth direction of said semiconductor substrate by anisotropic etching;

forming a sacrificed oxide film formed on an inner surface wall of each of the first trenches by thermal oxidation;

removing said sacrificed oxide film;

forming an insulation film in an interior of each of said first wenches;

filling each of the first trenches with a polycrystalline silicon film;

forming a plurality of second trenches in the second conductivity type region each positioned between an adjacent pair of said plurality of first trenches in parallel with said plurality of first trenches;

forming a second conductivity type protrusion region with a junction deeper than a junction of said second conductivity type region by introducing impurities of the second conductivity type from each of the second trenches by two or more ion implantation steps; and

forming a metal electrode so as to electrically connect said first conductivity type region with said second conductivity type protrusion region in each of the second trenches;

after each of the first trenches is filled wit the polycrystalline silicon film,

patterning said polycrystalline silicon film so that the patterned polycrystalline silicon film has a T-shaped cross section with a wider width than an opening of each of the first trenches;

forming a highly doped first conductivity type region inside said first conductivity type region at a portion from which said polycrystalline silicon film is removed, said highly doped first conductivity type region having a higher concentration than said first conductivity type region; and

forming a highly doped second conductivity type layer region inside said highly doped first conductivity type region at a portion between an adjacent two of said plurality of first trenches.

6. The method of manufacturing a semiconductor device according to claim 5, wherein at least one of said ion implantation steps is carried out at acceleration energy of 200 keV or higher.

7. The method of manufacturing a semiconductor device according to claim 5, wherein at least one of said ion implantation steps is carried out at acceleration energy of 30 keV or lower and a dose of implant ions at 1.0×

10¹⁵ (atoms/cm²) or more.

8. The method of manufacturing a semiconductor device according to claim 5, wherein the island of said second conductivity type region is formed by introducing impurities of a second conductivity type by two or more ion implantations.

9. A method of manufacturing a semiconductor device comprising:

forming a second conductivity type region in a semiconductor substrate having a principal surface of a first conductivity type;

forming a first conductivity type region inside said second conductivity type region, the first conductivity type region having a higher concentration than said semiconductor substrate;

forming a plurality of first trenches in a depth direction of said semiconductor substrate by anisotropic etching;

forming a sacrificed oxide film formed on an inner surface wall of each of the first trenches by thermal oxidation;

removing said sacrificed oxide film;

forming an insulation film in an interior of each of said first trenches;

filling each of the first trenches with a polycrystalline silicon film;

forming a plurality of second trenches in the second conductivity type region each positioned between an adjacent pair of said plurality of first trenches in parallel with said plurality of first trenches;

forming a second conductivity type protrusion region with a junction deeper than a junction of said second conductivity type region by introducing impurities of the second conductivity type from each of the second trenches by two or more ion implantation steps;

forming a metal electrode so as to electrically connect said first conductivity type region with said second conductivity type protrusion region in each of the second trenches;

forming a plurality of electric field alleviating regions by introducing impurities of the second conductivity type in a strip-wise shape so as to enclose a peripheral portion of said second conductivity type region;

forming a plurality of strip-wise highly doped second conductivity type regions each formed inside each of the electric field alleviating regions;

forming a plurality of strip-wise third trenches each formed inside each of the strip-wise second conductivity type regions in a depth direction of said semiconductor substrate by anisotropic etching;

forming a plurality of deeper second conductivity type regions each formed inside each of said third trenches by introducing impurities of the second conductivity type by two or more ion implantation steps;

forming a metal electrode which electrically connects each of said strip-wise second conductivity type region to each of said deeper second conductivity type region; and

forming a protection film at least on a surface of the semiconductor substrate except a region where said second conductivity type region underlies.

11. The method of manufacturing a semiconductor device according to claim 9, wherein each of said deeper second conductivity type region has a junction deeper than a junction of said second conductivity type region for forming a channel in a gate driving type power element having a high voltage withstanding characteristics.