Selective etch process for making a semiconductor device having a high-k gate dielectric

• US 7,037,845 B2
• Filed: 08/28/2003
• Issued: 05/02/2006
• Est. Priority Date: 08/28/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Turkot, Robert B. Jr.
• Primary Examiner(s): Chen, Kin-Chan
• Application Number:
  US10/652,546
• Publication Number:
  US 20050048791A1
• Time in Patent Office: 978 Days
• Field of Search: 438/706, 438/710, 438/714, 438/722, 438/745, 438/754, 438/756, 438/757
• US Class Current: 438/710
• CPC Class Codes: H01L 21/31111 by chemical means

Abstract

A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.

Claims

1. A method for making a semiconductor device comprising:

forming a high-k gate dielectric layer on a substrate; and

adding impurities to a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer, wherein the impurities comprise a halide.

2. The method of claim 1 wherein the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition, is between about 5 angstroms and about 40 angstroms thick, and comprises a material selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, and lead scandium tantalum oxide.

3. The method of claim 2 further comprising removing the first portion of the high-k gate dielectric layer selective to the second portion of the high-k gate dielectric layer.

4. The method of claim 3 wherein the first portion of the high-k gate dielectric layer is removed selectively to the second portion of the high-k gate dielectric layer by exposing the first portion of the high-k gate dielectric layer to an acid.

5. The method of claim 4 wherein the acid comprises a halide based acid.

6. The method of claim 4 wherein the acid comprises phosphoric acid.

7. The method of claim 1 wherein the impurities comprise a halogen.

8. The method of claim 1 wherein the adding the impurities to the first portion is performed by a plasma enhanced chemical vapor deposition process.

9. A method for making a semiconductor device comprising:

forming a high-k gate dielectric layer on a substrate;

forming a gate electrode on the high-k gate dielectric layer;

etching the gate electrode to expose a first portion of the high-k gate dielectric layer;

adding impurities to the first portion of the high-k gate dielectric layer, wherein a low power plasma enhanced chemical vapor deposition process is used to add impurities that comprise a mixture of a halogen and a halide; and

removing the first portion of the high-k gate dielectric layer selective to a second portion of the high-k gate dielectric layer.

10. The method of claim 9 wherein the gate electrode comprises polysilicon.

11. The method of claim 9 wherein the gate electrode is a metal gate electrode.

12. The method of claim 9 wherein the first portion of the high-k gate dielectric layer is removed selectively to the second portion of the high-k gate dielectric layer by exposing the first portion of the high-k gate dielectric layer to an acid that is selected from the group consisting of a halide based acid and phosphoric acid.

13. A method for making a semiconductor device comprising:

forming a high-k gate dielectric layer on a substrate;

forming a polysilicon based gate electrode on the high-k gate dielectric layer;

etching the polysilicon based gate electrode to expose a first portion of the high-k gate dielectric layer;

applying a plasma enhanced chemical vapor deposition process to add impurities to the first portion of the high-k gate dielectric layer; and

then

exposing the first portion of the high-k gate dielectric layer to an acid that is selected from the group consisting of a halide based acid and phosphoric acid.

14. A method for making a semiconductor device comprising:

forming a high-k gate dielectric layer on a substrate;

forming a polysilicon based gate electrode on the high-k gate dielectric layer;

etching the polysilicon based gate electrode to expose a first portion of the high-k gate dielectric layer;

applying a plasma enhanced chemical vapor deposition process to add impurities to the first portion of the high-k gate dielectric layer, wherein the plasma enhanced chemical vapor deposition process is performed at less than about 200 watts, and wherein the impurities comprise a mixture of a halogen and halide; and

then

exposing the first portion of the high-k gate dielectric layer to an acid that is selected from the group consisting of a halide based acid and phosphoric acid.

15. The method of claim 14 wherein the acid comprises hydrobromic acid or hydrochloric acid, and the impurities comprise a mixture of hydrogen bromide and chlorine.

16. The method of claim 15 wherein the first portion of the high-k gate dielectric layer is exposed to the acid at approximately room temperature for between about 5 minutes and about 30 minutes.

17. The method of claim 14 wherein the plasma enhanced chemical vapor deposition process is performed for less than about one minute.