Dual gate structure for a FET and method for fabricating same

• US 7,038,260 B1
• Filed: 03/04/2003
• Issued: 05/02/2006
• Est. Priority Date: 03/04/2003
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Lovoltech Incorporated
• Inventors: Yu, Ho-Yuan
• Primary Examiner(s): Coleman, W. David
• Assistant Examiner(s): NGUYEN, KHIEM D
• Application Number:
  US10/382,344
• Time in Patent Office: 1,155 Days
• Field of Search: 257/134, 257/135, 257/256, 257/264, 257/270, 257/278, 257/287, 257/504, 257/E29.314
• US Class Current: 257/287
• CPC Class Codes: H01L 29/66848 with a Schottky gate, i.e. MESFET
• CPC Class Codes: H01L 29/66909 Vertical transistors, e.g. tecnetrons
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/8124 with multiple gate
• CPC Class Codes: H01L 29/8128 with recessed gate

Abstract

A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches to adjust the lateral dimension for a first gate. Following the formation of the first gate by implantation or deposition, a buffer region is implanted below the first gate using a complementary dopant and a second sidewall spacer with a thickness that may be the same or greater than the thickness of the first sidewall spacer. Subsequent to the buffer implant, a second gate is implanted beneath the buffer layer using a third sidewall spacer with a greater thickness than the first sidewall spacer.

Claims

1. A junction field effect transistor (JFET) comprising:

a semiconductor substrate having a top surface and a bottom surface, wherein the top and bottom surfaces each comprise a heavily doped layer to provide an ohmic contact;

a first trench disposed in the top surface of said substrate;

a continuous first gate region formed in the bottom of said first trench, said first gate region continuous in a lateral direction parallel to said top surface;

a first buffer region formed beneath said first gate region;

a second gate region formed beneath said first buffer region, wherein said second gate region is formed beneath said first gate region that is continuous and is narrower than said first gate region, wherein said second gate region is continuous in said lateral direction;

a second trench disposed in the top surface of said substrate adjacent to said first trench;

a continuous third gate region formed in the bottom of said second trench, said third gate region continuous in said lateral direction;

a second buffer region formed beneath said third gate region; and

a fourth gate region formed beneath said second buffer region, wherein said fourth gate region is formed beneath said third gate region that is continuous and is narrower than said third gate region, wherein said fourth gate region is continuous in said lateral direction.

2. The JFET of claim 1, wherein said substrate is an n-type semiconductor substrate.

3. The JFET of claim 1, wherein said substrate is a p-type semiconductor substrate.

4. The JFET of claim 1, wherein said first gate region has a width that is substantially equal to a width of said first buffer region.

5. The JFET of claim 1, wherein said first gate region has a width that is less than a width of said first buffer region.

6. The JFET of claim 1, wherein a width of said second gate region is less than a width of said first buffer region.

7. The JFET of claim 1, wherein said substrate comprises a material selected from the group consisting of silicon, gallium arsenide, silicon carbide, and gallium nitride.

8. A metal-semiconductor field effect transistor (MESFET) comprising:

a semiconductor substrate having a top surface and a bottom surface, wherein the top and bottom surfaces each comprise a heavily doped layer to provide an ohmic contact;

a first trench disposed in the top surface of said substrate;

a continuous first gate region formed on the bottom of said first trench, said first gate region continuous in a lateral direction parallel to said top surface;

a first buffer region formed beneath said first gate region;

a second gate region formed beneath said first buffer region, wherein said second gate region is formed beneath said first gate region that is continuous and is narrower than said first gate region, wherein said second gate region is continuous in said lateral direction;

a second trench disposed in the top surface of said substrate adjacent to said first trench;

a continuous third gate formed in the bottom of said second trench, said third get region continuous in said lateral direction;

a second buffer region formed beneath said third gate region; and

a fourth gate region formed beneath said second buffer region, wherein said fourth gate region is formed beneath said third gate region that is continuous and is narrower than said third gate region, wherein said fourth gate region is continuous in said lateral direction.

9. The MESFET of claim 8, wherein said substrate is an n-type semiconductor substrate.

10. The MESFET of claim 8, wherein said substrate is a p-type semiconductor substrate.

11. The MESFET of claim 8, wherein said first gate region has a width that is substantially equal to a width of said first buffer region.

12. The MESFET of claim 8, wherein said first gate region has a width that is less than a width of said first buffer region.

13. The MESFET of claim 8, wherein a width of said second gate region is less than a width of said first buffer region.

14. The MESFET of claim 8, wherein said substrate comprises a material selected from the group consisting of silicon, gallium arsenide, silicon carbide, and gallium nitride.