Integrated circuit device

• US 7,038,290 B1
• Filed: 06/07/1995
• Issued: 05/02/2006
• Est. Priority Date: 09/28/1965
• Status: Expired due to Fees

• Current Assignee: LI Second Family Limited Partnership
• Original Assignee: LI Second Family Limited Partnership
• Inventors: Li, Chou H.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US08/483,938
• Time in Patent Office: 3,982 Days
• Field of Search: 257/506, 257/509, 257/515
• US Class Current: 257/506
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/7621 the recessed region having a shape other than rectangular, e.g. rounded or oblique shape H01L21/76208 takes precedence
• CPC Class Codes: H01S 5/02461 Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
• CPC Class Codes: H01S 5/0424 lateral current injection
• CPC Class Codes: H01S 5/183 having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
• CPC Class Codes: H01S 5/2045 employing free standing waveguides or air gap confinement
• CPC Class Codes: H01S 5/2072 obtained by vacancy induced diffusion

Abstract

An integrated circuit device comprising:

• • a body of a first solid material having an upper surface and a major bottom surface;
  • a pocket of a second solid material having a top surface and a side surface, and a bottom surface which contacts a selected portion of said upper surface on said body;
  • said first and second solid materials being so selected as to form, where said pocket contacts said body at said selected portion of said upper surface, an electronic interfacial barrier which is substantially conductive under an applied bias of at least one selected polarity; and
  • a solid electrically insulating region which meets said barrier and adjoins both said body and at least a line on said side surface of said pocket;
  • wherein at least a part of said solid electrically insulating region comprises nitrogen located at least below the level of said electronic interfacial barrier.

Claims

1. A solid state semiconductor device comprising:

a first solid semiconductor material of one conductivity type, a second solid semiconductor material of an opposite conductivity type, said first and second solid semiconductor materials having respective adjoining regions, and a PN junction between said respective adjoining regions; and

an electrically insulating solid material which adjoins said first solid semiconductor material, said second solid semiconductor material, and a lateral edge of said PN junction;

said electrically insulating solid material having a top curved interface with a radius of curvature selected from the group consisting of 0.001 cm, 0.01 cm, 0.1 cm, and 1.0 cm;

said first solid semiconductor material having a first portion which is above said PN junction and has a thickness which gradually changes with closeness in a lateral direction to said lateral edge of said PN junction;

said second solid semiconductor material having a first portion which is underneath said PN junction and has a thickness which gradually changes with closeness in a lateral direction to said lateral edge of said PN junction direction; and

said electrically insulating material having a first portion which is laterally spaced from said PN junction and has a thickness which gradually decreases with closeness in a lateral direction to said lateral edge of said PN junction.

2. A solid state semiconductor device as in claim 1 in which:

said first solid semiconductor material has a first portion which is above said PN junction and has a thickness which gradually changes with closeness in a lateral direction to said lateral edge of sand PN junction; and

wherein

said first solid semiconductor material also has a second portion which is above said PN junction, is laterally spaced from said lateral edge of said PN junction, and is uniform in thickness.

3. A solid state semiconductor device as in claim 2, in which said electrically insulating material is an intrinsic semiconductor over 99.999% of which is a selected semiconductor and having few doping impurities and free electrons and holes to conduct electricity thereby having the resistivity or conductivity of that of a conventional insulating material.

4. A solid state semiconductor device comprising:

a first solid semiconductor material of one conductivity type, a second solid semiconductor material of an opposite conductivity type, said first and second solid semiconductor materials being at respective adjacent regions thereof, and

an electronic signal-translating, rectifying barrier between said respective adjacent regions, said rectifying barrier having a lateral edge;

an electrically insulating solid material which adjoins said first solid semiconductor material, said second solid semiconductor material, and said lateral edge of said PN junction; and

at least one of said first solid semiconductor material, said second solid semiconductor material, and said electrically insulating solid material having a designated first portion which has a thickness changing gradually along a selected lateral direction;

said second solid semiconductor material having a first portion which has a thickness changing gradually along a second lateral direction;

said electrically insulating solid material having a first portion which has a thickness changing gradually along a third lateral direction.

5. A solid state semiconductor device as in claim 4 in which:

said rectifying barrier has a thickness gradually increasing in a lateral direction from a selected lateral edge thereof toward its center.

6. A solid state semiconductor device as in claim 5 in which:

a radius of curvature of said rectifying barrier gradually decreases along a lateral direction from a center thereof towards either one of its left or right edge.

7. A solid state semiconductor device as in claim 4 in which:

the thickness of said first portion of said first solid semiconductor material and the thickness of said first portion of said second solid semiconductor material change in a complementary manner such that where one increases the other decreases.

8. A solid state semiconductor device as in claim 7 in which:

said first portion of said first solid semiconductor material adjoins and is above said PN junction, including above said cured portion of said PN junction.

9. A solid state semiconductor device as in claim 4 in which:

at least one of said first solid semiconductor material, said second solid semiconductor material, and said electrically insulating solid material has a respective selected portion thereof which is laterally spaced from said lateral edge of said PN junction and has a uniform thickness.

10. A solid state semiconductor device as in claim 4 in which:

at least one said first solid semiconductor material and said electrically insulating material consists essentially of a solid intrinsic semiconductor.

11. An active semiconductor device of less than one micron in size and having a vertical depth accuracy of better than 1,300 Angstroms, comprising:

a semiconductor substrate having one conductivity type;

a semiconductor pocket positioned adjacently on said substrate and having an opposite conductivity type;

an electronic signal-translating, rectifying barrier adjoining and forming as its top with, said pocket and adjoining and forming at its bottom with, said substrate;

said rectifying barrier having a lateral edge; and

an electrically isolating solid material which adjoins and metallurgically perfectly bonds with all said substrate, said pocket, and said lateral edge of said rectifying barrier;

with respective, nearly 100% dense bonding regions which are microscopically free of visible microcracks at 1,000 times magnification;

said barrier region having a selected surface which is microscopically precise, with a better than one micron in accuracy in shape, size, and position of the rectifying barrier;

on a vertical cross-section, said barrier region having a curved portion in a major central portion thereof.

12. An active semiconductor device as in claim 11 wherein at least one of said substrate, said pocket, and said rectifying barrier contains moderate, residual beneficial stresses to improve device performance.

13. An active semiconductor device as in claim 11 including means for beneficially stressing at least one of said substrate, said pocket, and said rectifying barrier to improve device performance.

14. An active semiconductor device as in claim 11 wherein at least one of said substrate, said pocket, and said rectifying barrier is an intrinsic semiconductor consisting essentially of a semiconductor material but having others of magnitude less doping impurities and free electrons and holes to conduct electricity so that the intrinsic semiconductor is orders of magnitude less electrically conductive than the doped semiconductor pocket and substrate of the device.

15. An active semiconductor devices as in claim 11 wherein at least one of said substrate, said pocket, and said rectifying barrier is of a semiconductor material selected from the group consisting of Si, Ge, GaAs, GaP, InP, In, Sb, and other III–

V compounds, IV–

VI compounds and

said electronically signal-translating, rectifying barrier is selected from the group consisting of PN junction, metal-oxide barrier, metal-semiconductor barrier, oxide-semiconductor barrier, heterojunction between different semiconductors, and other optoelectromagnetically active signal translating region.

16. An active semiconductor device as in claim 11 including a rapid, fluid cooling jet to cool at least one of said substrate, said pocket, and said rectifying barrier;

and

including means for regulated optoelectromagnetic interaction of the signal-rectifying barrier with an object selected from the group consisting of ambient and contact material.

17. An active semiconductor device as in claim 11 including means for introducing a rapidly moving cooling fluid jet tangentially against a surface of interface of at least one of said semiconductor pocket and said rectifying barrier to insure efficient surface cooling of the device.

18. An active semiconductor device as in claim 11 wherein for said electrically insulating solid material, silicon nitride is used predominantly over silicon dioxide, because the linear expansion of silicon is 29.2% for in-situ oxidation from silicon dioxide but only 4.3% from silicon to silicon to Si3, N4, resulting in much less thermal mismatch stresses for silicon nitride than silicon dioxide.

19. An active semiconductor device as in claim 11 having a non-planar top surface.

20. An active semiconductor device as in claim 11 wherein a doped semiconductor pocket of a semiconductor material sits on top of a undoped, intrinsic semiconductor of the same silicon semiconductor material.