Shift resister and liquid crystal display having the same

• US 7,038,653 B2
• Filed: 06/04/2003
• Issued: 05/02/2006
• Est. Priority Date: 09/05/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Moon, Seung-Hwan
• Primary Examiner(s): Lefkowitz, Sumati
• Assistant Examiner(s): Xiao, Ke
• Application Number:
  US10/454,331
• Publication Number:
  US 20040046729A1
• Time in Patent Office: 1,063 Days
• Field of Search: 345/98, 345/100, 345/559, 377/64, 377/81, 365/78, 365 80- 93
• US Class Current: 345/100
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

In a shift register and an LCD having the same, the shift register includes stages having odd stages for receiving a first clock signal and even stages for receiving a second clock signal and all stages receive a control signal. Each of the stages includes a pull-up section for providing one of first and second clock signals to an output terminal, a pull-down section for providing a first power voltage to the output terminal, a pull-up driving section for turning on/off the pull-up section in response to the control signal, a first pull-down driving section for outputting a second control signal, and a second pull-down driving section for turning off the pull-down section in response to the input signal and turning on the pull-down section in response to the second control signal.

Claims

1. A shift register in which a plurality of stages are connected one after another to each other, the stages having a first stage in which a start signal is coupled to an input terminal of the first stage, the shift register sequentially outputting output signals of each of the stages, each of the stages receiving one of a plurality of clock signals and a plurality of control signals, the one of the plurality of control signals controlling output of said one of the plurality of clock signals,

each of the stages comprising:

a pull-up section to provide said one of the plurality clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a front edge of an output signal of one of previous stages and to turn off the pull-up section in response to a front edge of said one of the plurality of control signals;

a pull-down section to provide a first power voltage to the output terminal;

a first pull-down driving section to output a second control signal in response to turn-on of the pull-up section; and

a second pull-down driving section to turn off the pull-down section in response to a front edge of an input signal and to turn on the pull-down section in response to the second control signal.

2. The shift register of claim 1, wherein the pull-up driving section comprises:

a capacitor connected between the input node of the pull-up section and the output terminal;

a first transistor of which a first current electrode is coupled to a second power voltage node, a control electrode coupled to the input terminal, and a second current electrode is coupled to the input node of the pull-up section;

a second transistor of which a first current electrode coupled to the input node of the pull-up section, a control electrode is coupled to the input node of the pull-down section and a second current electrode is coupled to the first power voltage; and

a third transistor of which a first current electrode coupled to the input node of the pull-up section, a control electrode is coupled to an output terminal of one of next stages and a second current electrode is coupled to the first power voltage node.

3. The shift register of claim 1, wherein the first pull-down driving section comprises:

a first transistor of which a first current electrode and a control electrode are commonly coupled to a second power voltage node;

a second transistor of which a first current electrode is coupled to a second electrode of the fourth transistor, a control electrode is coupled to the input signal, and a second current electrode is coupled to the first power voltage node.

4. The shift register of claim 3, wherein a channel width ratio of the first transistor to the second transistor is approximately 1:

1 and a channel length ratio of the fourth transistor to the fifth transistor is approximately 1;

2.

5. The shift register of claim 1, wherein the second pull-down driving section comprises;

a third transistor of which a first current electrode is coupled to a second power voltage node, a control electrode is coupled to an output signal of the first pull-down driving section and a second current electrode is coupled to the input node of the pull-down section; and

a fourth transistor of which a first current electrode is coupled to the input node of the pull-down section, a control electrode is coupled to the input signal and a second current electrode is coupled to the first power voltage node.

6. The shift register of claim 5, wherein a channel width ratio of the third transistor to the fourth transistor is approximately 1:

1.

8. The shift register of claim 1, wherein odd numbered stages respectively receive a first clock signal and even numbered stages respectively received a second clock signal having a phase opposite to the first clock signal.

9. The shift register of claim 1, wherein the pull-up driving section is coupled to an input node of the pull-up section.

10. The shift register of claim 1, wherein the first pull-down driving section is coupled to an input node of the pull-up section.

11. The shift register of claim 1, wherein the second pull-down driving section is coupled to an input node of the pull-down section.

7. A display device comprising a display cell array circuit, a scan driving circuit formed on a substrate, the display cell array circuit comprising a plurality of data lines and a plurality of gate lines, each of the display cell arrays coupled to a corresponding pair of data line and gate line,

the scan driving circuit comprising a shift register including a plurality of stages coupled one after another to each other, the stages having a first stage in which a start signal is coupled to an input terminal, for sequentially outputting output signals of respective stages, each of the stages receiving one of a plurality of clock signals and one of a plurality of control signals, the one of the plurality of control signals controlling output of said one of the plurality of clock signals,

wherein each of the stages comprises:

a pull-up section to provide said one of the plurality of clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a front edge of an output signal of one of previous stages and to turn off the pull-up section in response to a front edge of the said one of the plurality of control signals;

a pull-down section to provide a first power voltage to the output terminal;

a first pull-down driving section to a second control signal in response to turn-on of the pull-up section;

a second pull-down driving section to turn off the pull-down section in response to a previous a edges of an input signal and to turn on the pull-down section in response to the second control signal.

19. The display device of claim 7, wherein odd numbered stages respectively received a first clock signal and even numbered stages respectively received a second clock signal having a phase opposite to the first clock signal.

20. The display device of claim 7, wherein the pull-up driving section is coupled to an input node of the pull-up section, the first pull-down driving section is coupled to an input node of the pull-up section, and the second pull-down driving section is coupled to an input node of the pull-down section.

12. A scan driver in which a plurality of stages are connected one after another to each other, the stages having a first stage in which a start signal is coupled to an input terminal of the first stage, the shift register sequentially outputting output signals of each of the stages, each of the stages receiving one of a plurality of clock signals and one of a plurality of controls signals, the one of the plurality of control signals controlling output of said one of plurality of the clock signals,

each of the stages comprising:

a pull-up section to f provide said one of the plurality of clock signals to an output terminal;

a pull-up driving section to turn on the pull-up section in response to a front edge of an output signal of one of previous stages and to turn off the pull-up section in response to a front edge of said one of the plurality of control signals;

a pull-down section to provide a first power voltage to the output terminal;

a first pull-down driving section to output a second control signal in response to turn-on of the pull-up section; and

a second pull-down driving section to turn off the pull-down section in response to a front edge of an input signal and to turn on the pull-down section in response to the second control signal.

13. The scan driver of claim 12, wherein odd numbered stages respectively receive a first clock signal and even numbered stages respectively received a second clock signal having a phase opposite to the first clock signal.

14. The shift register of claim 12, wherein the pull-up driving section comprises:

a capacitor connected between the input node of the pull-up section and the output terminal;

a first transistor of which a first current electrode is coupled to a second power voltage node, a control electrode coupled to the input terminal, and a second current electrode is coupled to the input node of the pull-up section;

a second transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to the input node of the pull-down section and a second current electrode is coupled to the first power voltage; and

a third transistor of which a first current electrode is coupled to the input node of the pull-up section, a control electrode is coupled to an output terminal of one of next stages and a second current electrode is coupled to the first power voltage.

15. The scan driver of claim 12, wherein the first pull-down driving section comprises:

a first transistor of which a first current electrode and a control electrode are commonly coupled to a second power voltage node;

a second transistor of which a first current electrode is coupled to a second electrode of the fourth transistor, a control electrode is coupled to the input signal, and a second current electrode is coupled to the first power voltage node.

16. The scan driver of claim 15, wherein a channel width ratio of the first transistor to the second transistor is approximately 1:

1 and a channel length ratio of the fourth transistor to the fifth transistor is approximately 1;

2.

17. The shift register of claim 15, wherein the second pull-down driving section comprises:

a third transistor of which a first current electrode is coupled to a second power voltage node, a control electrode is coupled to an output signal of the first pull-down driving section and a second current electrode is coupled to the input node of the pull-down section; and

a fourth transistor of which a first current electrode is coupled to the input node of the pull-down section, a control electrode is coupled to the input signal and a second current electrode is coupled to the first power voltage node.

18. The scan driver of claim 17, wherein a channel width ratio of the third transistor to the fourth transistor is approximately 1:

1.