Dynamic memory word line driver scheme

• US 7,038,937 B2
• Filed: 03/02/2004
• Issued: 05/02/2006
• Est. Priority Date: 04/06/1990
• Status: Expired due to Fees

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Lines, Valerie L.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Luu, Pho M.
• Application Number:
  US10/791,437
• Publication Number:
  US 20050018523A1
• Time in Patent Office: 791 Days
• Field of Search: 365/154, 365/189.11, 365/185.26, 365/149, 365/150, 365/189.12, 365/230.01
• US Class Current: 365/154
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels V_ss and V_dd, and for providing a select signal at levels V_ss and V_dd, a high voltage supply source V_pp which is higher in voltage than V_dd, a circuit for translating the select signals at levels V_ss and V_dd to levels V_ss and V_pp and for applying it directly to the word lines whereby an above V_dd voltage level word line is achieved without the use of double boot-strap circuits.

Claims

1. A method of selecting a word line in a dynamic random access memory to store a voltage level in a memory cell comprising:

coupling a controlled high supply voltage level that is greater than the voltage level stored in the memory cell to a level shifter circuit, the level shifter circuit comprising a pair of cross-coupled transistors connected drain-to-gate and having respective sources coupled to the controlled high supply voltage;

coupling a logic signal having only logic levels that are less than the controlled high supply voltage level to the level shifter circuit to produce a control signal having a logic state at the controlled high supply voltage level; and

driving a selected word line to the controlled high supply voltage level in response to the control signal.