Phase change resistor cell and nonvolatile memory device using the same

• US 7,038,938 B2
• Filed: 06/30/2004
• Issued: 05/02/2006
• Est. Priority Date: 12/13/2003
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Graham, Kretelia
• Application Number:
  US10/879,140
• Publication Number:
  US 20050128791A1
• Time in Patent Office: 671 Days
• Field of Search: 365/154
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode

Abstract

A nonvolatile memory device features a phase change resistor cell. More specifically, a phase change resistor and a hybrid switch which does not require an additional gate control signal are used to embody rapid nonvolatile SRAM characteristics. In the nonvolatile memory device, a cell plate is connected to a top electrode of a nonvolatile resistor memory device whose resistance state is changed by current values, and the hybrid switch is connected between a flip-flop and a bottom electrode of the nonvolatile resistor memory device, thereby improving characteristics of the rapid nonvolatile memory.

Claims

1. A phase change resistor cell comprising:

a plurality of phase change resistors for storing at least one or more of data corresponding to a crystallization state changed by current applied from a cell plate line;

a plurality of hybrid switches connected one by one to the plurality of phase change resistors, and selectively switched depending on voltages applied to the cell plate line and a bit line; and

a storage means, connected to the plurality of hybrid switches, for storing different nonvolatile data through input/output terminals.

2. The phase change resistor cell according to claim 1, wherein each of the plurality of hybrid switches is switched when a voltage applied to the cell plate line is a first voltage at a power-up mode, and outputs data stored in the plurality of phase change resistors to the storage means.

3. The phase change resistor cell according to claim 2, wherein each of the plurality of hybrid switches is switched when a voltage applied to the cell plate line is a negative trigger voltage lower than the first voltage by a threshold voltage at a write mode, and outputs data applied from the bit line to the plurality of phase change resistors.

4. The phase change resistor cell according to claim 3, wherein after the negative trigger voltage is applied, a voltage level of the bit line drops step by step when data of the bit line are at a high level, and a voltage level of the bit line is constantly maintained when data of the bit line is at a low level.

5. The phase change resistor cell according to claim 1, further comprising an access regulating unit for controlling connection between the bit line and the storage means depending on a voltage level of a word line.

6. The phase change resistor cell according to claim 5, wherein the access regulating unit comprises:

a first driving unit for controlling connection between a bit line and a first node of the storage means depending on the level of the voltage applied to the word line; and

a second driving unit for controlling connection between a bit line bar and a second node of the storage means depending on the level of the voltage applied to the word line.

7. The phase change resistor cell according to claim 1, wherein each of the plurality of hybrid switches comprises a PN diode switch and a PNPN diode switch which are connected in parallel between the plurality of phase change resistors and the storage means.

8. The phase change resistor cell according to claim 7, wherein the PN diode switch consists of a P-type region connected to the phase change resistor and a N-type region connected to the storage means.

9. The phase change resistor cell according to claim 7, wherein the PNPN diode switch consists of an upper N-type region connected to the phase change resistor and a lower P-type region connected to the storage means.

10. The phase change resistor cell according to claim 1, wherein the storage means is flip-flop unit.

11. The phase change resistor cell according to claim 10, wherein the flip-flop unit comprises:

a PMOS latch located between a power voltage terminal and the input/output terminals to have a cross-coupled structure; and

a NMOS latch located between a ground voltage terminal and the input/output terminals to have a cross-coupled structure.

12. The phase change resistor cell according to claim 11, wherein the flip-flop unit comprises:

a third driving unit, connected between the power voltage terminal and the flip-flop unit, having a gate to receive a first sense amplifier enable signal; and

a fourth driving unit, connected between the ground voltage terminal and the flip-flop unit, having a gate to a second sense amplifier enable signal having an opposite phase to that of the first sense amplifier enable signal.

13. A nonvolatile memory device using a phase change resistor cell, comprising:

a plurality of phase change resistor cell arrays each comprising a plurality of unit phase change resistor cells arranged in row and column directions; and

a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of phase change resistor cell arrays,

wherein each of the plurality of unit phase change resistor cells comprises;

a plurality of phase change resistors for storing at least one or more of data corresponding to a crystallization state changed by current applied from a cell plate line;

a plurality of hybrid switches connected one by one to the plurality of phase change resistors, and selectively switched depending on voltages applied to the cell plate line and a bit line; and

a storage means, connected to the plurality of hybrid switches, for storing different nonvolatile data through nodes of both terminals.

14. The nonvolatile memory device according to claim 13, further comprising:

a plurality of word line driving units for selectively driving word lines of the plurality of phase change resistor cell arrays;

a plurality of cell plate line driving units for selectively driving cell plate lines of the plurality of phase change resistor cell arrays;

a data bus shared by the plurality of sense amplifiers;

a data buffer for buffering data applied from the data bus; and

an input/output port for externally outputting output data applied from the data buffer or applying input data applied externally to the data buffer.

15. The nonvolatile memory device according to claim 13, wherein each of the plurality of phase change resistor cell arrays further comprises:

a power-up reset unit for outputting a reset signal for initializing the plurality of phase change resistor cell arrays;

a read/write control unit for outputting control signals for reading/writing data in the plurality of phase change resistor cell arrays; and

a phase change resistor cell control unit for controlling read/write operations of the phase change resistor cell array in response to the reset signal and the control signals.

16. The nonvolatile memory device according to claim 13, wherein each of the phase change resistor cells is located where a plurality of word lines, a plurality of cell plate lines, a power voltage terminal and a ground voltage terminal which are arranged in a row direction are crossed with a pair of bit lines which are arranged in a column direction.

17. The nonvolatile memory device according to claim 13, wherein each of the plurality of unit phase change resistor cells is located where a plurality of word lines, a plurality of cell plate lines, a plurality of sense amplifier enable signal terminals which are arranged in a row direction are crossed with a pair of bit lines which are arranged in a column direction.

18. The nonvolatile memory device according to claim 13, wherein each of the plurality of sense amplifiers is connected to the paired bit lines, and amplifies a voltage applied from the paired bit lines when a sense amplifier enable signal is activated.

19. The nonvolatile memory device according to claim 13, wherein the unit phase change resistor cell further comprises an access regulating unit for controlling connection between the bit line and the storage means depending on a level of a voltage applied to a word line.

20. The nonvolatile memory device according to claim 13, wherein each of the plurality of hybrid switches comprises a PN diode switch and a PNPN diode switch which are connected in parallel between the plurality of phase change resistors and the storage means.

21. The nonvolatile memory device according to claim 20, wherein the PN diode switch consists of a P-type region connected to the phase change resistor and a N-type region connected to the storage means.

22. The nonvolatile memory device according to claim 20, wherein the PNPN diode switch consists of an upper N-type region connected to the phase change resistor and a lower P-type region connected to the storage means.