Programmable transmission and reception of out of band signals for serial ATA
First Claim
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1. An apparatus comprising:
- a plurality of writeable registers configured to store (i) a first burst value and (ii) a first gap value;
a control circuit configured to generate an idle signal (i) in a transmit state for a first duration determined by said first burst value and (ii) in an idle state for a second duration determined by said first gap value in response to a first command signal; and
a transmitter circuit configured to (i) enable transmitting while said idle signal is in said transmit state and (ii) disable transmitting while said idle signal is in said idle state.
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Abstract
An apparatus generally comprising a plurality of writeable registers, a control circuit, and a transmitter circuit. The writeable registers may be configured to store (i) a first burst value and (ii) a first gap value. The control circuit may be configured to generate an idle signal (i) in a transmit state for a first duration determined by the first burst value and (ii) in an idle state for a second duration determined by the first gap value in response to a first command signal. The transmitter circuit may be configured to (i) enable transmitting while the idle signal is in the transmit state and (ii) disable transmitting while the idle signal is in the idle state.
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Citations
20 Claims
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1. An apparatus comprising:
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a plurality of writeable registers configured to store (i) a first burst value and (ii) a first gap value; a control circuit configured to generate an idle signal (i) in a transmit state for a first duration determined by said first burst value and (ii) in an idle state for a second duration determined by said first gap value in response to a first command signal; and a transmitter circuit configured to (i) enable transmitting while said idle signal is in said transmit state and (ii) disable transmitting while said idle signal is in said idle state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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a plurality of writeable registers configured to store (i) a first burst value and (ii) a first gap value; a receiver circuit configured to generate a status signal having a loss state and a presence state in response to a received signal; and a control circuit configured to generate a first detection signal in response to detecting a predetermined number of valid bursts each separated by a valid gap in said status signal, wherein (i) each said valid burst has a first duration in said presence state proportional to said first burst value and (ii) said each valid gap has a second duration in said loss state proportional to said first gap value. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. An apparatus comprising:
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means for writeably storing (i) a first burst value and (ii) a first gap value; means for generating an idle signal (i) in a transmit state for a first duration determined by said first burst value and (ii) in an idle state for a second duration determined by said first gap value in response to a first command signal; and means for (i) enabling transmitting while said idle signal is in said transmit state and (ii) disabling transmitting while said idle signal is in said idle state.
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Specification