Delay locked loop circuitry for clock delay adjustment

• US 7,039,147 B2
• Filed: 02/14/2003
• Issued: 05/02/2006
• Est. Priority Date: 02/06/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kim, Jun, Lee, Thomas H., Stark, Donald C., Johnson, Mark G., Garlepp, Bruno W., Horowitz, Mark A., Lau, Benedict C., Donnelly, Kevin S., Yu, Leung, Chau, Pak Shing, Nguyen, Nhat M., Chan, Yiu-Fai, Tran, Chanh Vi
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US10/366,865
• Publication Number:
  US 20040223571A1
• Time in Patent Office: 1,173 Days
• Field of Search: 375/354, 375/358, 375/371, 375/373, 375/375, 375/376, 327/5, 327/141, 327/163, 327/261, 327/276, 327/149, 327/156, 327/158, 327/161, 331/14, 331/17, 331/25
• US Class Current: 375/373
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

Claims

1. A clock alignment system, comprising:

a receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock;

a first delay-locked loop configured to generate a plurality of phase vectors from a first reference clock; and

a second delay-locked loop coupled to the first delay-locked loop and configured to generate the receive clock from a set of phase vectors selected from the plurality of phase vectors and a second reference clock, wherein the second reference clock is distinct from the first reference clock.

2. The system of claim 1, wherein the second delayed-lock loop is configured to generate a substantially zero degree phase relationship between the second reference clock and the receive clock.

3. The system of claim 1, wherein the first and second reference clocks are derived from the same clock source.

4. The system of claim 1, wherein the system is part of a graphics engine.

5. The system of claim 1, wherein the first delay-locked loop further comprises:

a first adjustable delay circuit coupled to the first reference clock and a delay adjustment signal, the first adjustable delay circuit configured to provide phase vectors based at least in part on the delay adjustment signal;

a first phase detector coupled to the first reference clock and the first adjustable delay circuit, the first phase detector configured to provide a first phase difference signal indicative of the phase difference between the first reference clock and a respective phase vector; and

a first control circuit coupled to the first phase detector and configured to provide the delay adjustment signal based on the first phase difference signal.

6. The system of claim 5, wherein the second delay-locked loop further comprises:

a selection circuit adapted to receive phase vectors from the first delay-locked loop and configured to select the set of phase vectors in response to a selection signal;

a phase interpolator coupled to the selection circuit and a second phase adjustment signal, the phase interpolator configured to use the second phase adjustment signal at least in part to provide an output clock which is in phase with one of the selected phase vectors;

a second adjustable delay circuit coupled to the phase interpolator and the delay adjustment signal provided by the first delay-locked loop and configured to generate a feedback clock based at least in part on the delay adjustment signal;

a second phase detector coupled to receive the second reference clock and the feedback clock and configured to provide a phase difference between the second reference clock and the feedback clock; and

a second control circuit coupled to the second phase detector and configured to provide the selection signal and the phase adjustment signal to the selection circuitry and phase interpolator, respectively, based at least in part on the phase difference between the second reference clock and the feedback clock.

7. The system of claim 6, further comprising:

a trim adjustment circuit coupled to the delay adjustment signal and configured to bias the delay adjustment signal so as to increase or decrease the amount of delay provided by the second adjustable delay circuit.

8. The system of claim 7, wherein the trim adjustment circuit biases the delay adjustment signal with an analog signal derived from a digital-to-analog converter and a digital representation of a trim value.

9. A clock alignment system, comprising:

a transmitter adapted to be coupled to a data bus and configured to transmit data in accordance with a transmit clock;

a first delay-locked loop configured to generate a plurality of phase vectors from a reference clock; and

a second delay-locked loop coupled to the first delay-locked loop and configured to generate the transmit clock from a set of phase vectors selected from the plurality of phase vectors and an input clock, wherein the input clock is distinct from the reference clock.

10. The system of claim 9, wherein the second delayed-lock loop is configured to generate a substantially ninety degree phase relationship between the reference clock and the transmit clock.

11. The system of claim 9, wherein the system is part of a graphics engine.

12. The system of claim 9, wherein the first delay-locked loop further comprises:

a first adjustable delay circuit coupled to the reference clock and a delay adjustment signal, the first adjustable delay circuit configured to provide phase vectors based at least in part on the delay adjustment signal;

a first phase detector coupled to the reference clock and the first adjustable delay circuit, the first phase detector configured to provide a phase difference signal indicative of the phase difference between the reference clock and a respective phase vector; and

a first control circuit coupled to the first phase detector and configured to provide the delay adjustment signal based on the phase difference signal.

13. The system of claim 12, wherein the second delay-locked loop further comprises:

a selection circuit adapted to receive phase vectors from the first delay-locked loop and configured to select the set of phase vectors in response to a selection signal;

a phase interpolator coupled to the selection circuit and a phase adjustment signal, the phase interpolator configured to use the phase adjustment signal at least in part to provide an output clock which is in phase with one of the selected phase vectors;

a second adjustable delay circuit coupled to the phase interpolator and the delay adjustment signal provided by the first delay-locked loop and configured to generate a feedback clock based at least in part on the delay adjustment signal;

a second phase detector coupled to receive the input clock and the feedback clock and configured to provide a phase difference between the input clock and the feedback clock; and

a second control circuit coupled to the second phase detector and configured to provide the selection signal and the phase adjustment signal to the selection circuitry and phase interpolator, respectively, based at least in part on the phase difference between the input clock and the feedback clock.

14. The system of claim 13, further comprising:

a trim adjustment circuit coupled to the delay adjustment signal and configured to bias the delay adjustment signal so as to increase or decrease the amount of delay provided by the second adjustable delay circuit.

15. The system of claim 14, wherein the trim adjustment circuit biases the delay adjustment signal with an analog signal derived from a digital-to-analog converter and a digital representation of a trim value.

16. A clock alignment system including a master device and a slave device adapted to be coupled to a data bus and clock lines, comprising:

a master device including a first receiver, comprising;

a first delay-locked loop configured to generate a plurality of phase vectors from a first reference clock received from a first clock line; and

a second delay-locked loop coupled to the first delay-locked loop and configured to generate a first receive clock from a set of phase vectors selected from the plurality of phase vectors and a second reference clock from a second clock line, wherein the second delayed-lock loop is configured to generate a substantially zero degree phase relationship between the second reference clock and the first receive clock; and

a slave device including a second receiver, comprising;

a third delay-locked loop configured to generate another plurality of phase vectors from a third reference clock received from a third clock line; and

a fourth delay-locked loop coupled to the third delay-locked loop and configured to generate a second receive clock from an additional two phase vectors selected from the another plurality of phase vectors and a fourth reference clock received from a fourth clock line, wherein the fourth delayed-lock loop is configured to generate a substantially zero degree phase relationship between the fourth reference clock and the second receive clock.

17. The system of claim 16, wherein the master device includes a transmitter coupled to the second delay-locked loop and configured to generate a substantially 90 degree phase relationship between the first reference clock and a first transmit clock.

18. The system of claim 16, wherein the slave device includes a transmitter coupled to the fourth delay-locked loop and configured to generate a substantially 90 degree phase relationship between the third reference clock and a second transmit clock.

19. The system of claim 16, wherein the first, second, third and fourth reference clocks are derived from the same clock source.

20. The system of claim 16, wherein the master device and slave device are separate integrated circuit chips.

21. A clock alignment system including a first integrated circuit device and a second integrated circuit device, the second integrated circuit device comprising:

a selection circuit adapted to receive phase vectors from the first integrated circuit device and configured to select a set of phase vectors in response to a selection signal;

a phase interpolator coupled to the selection circuit and a phase adjustment signal, the phase interpolator configured to use the phase adjustment signal at least in part to provide an output clock which is in phase with one of the selected phase vectors;

an adjustable delay circuit coupled to the phase interpolator and a delay adjustment signal from the first integrated circuit device and configured to generate a feedback clock based at least in part on the delay adjustment signal;

a phase detector coupled to receive an input clock and the feedback clock and configured to provide a phase difference between the input clock and the feedback clock; and

a control circuit coupled to the phase detector and configured to provide the selection signal and the phase adjustment signal to the selection circuitry and phase interpolator, respectively, based at least in part on the phase difference between the input clock and the feedback clock.

22. The system of claim 21, further comprising:

a trim adjust circuit coupled to the delay adjustment signal and configured to bias the delay adjustment signal so as to increase or decrease the amount of delay provided by the adjustable delay circuit.

23. The system of claim 22, wherein the trim adjustment circuit biases the delay adjustment signal with an analog signal derived from a digital-to-analog converter and a digital representation of a trim value.

24. The system of claim 21, wherein the adjustable delay circuit further comprises:

a first adjustable delay section having a first predetermined number of delay elements;

a second adjustable delay section having a second predetermined number of delay elements, wherein the first predetermined number of delay elements is greater than the second predetermined number of delay elements; and

circuitry for selecting between the first and second adjustable delay sections so as to provide a phase lead or lag between the input clock and the output clock.

25. The system of claim 21, wherein the control circuit is configured to adjust the phase adjustment signal in response to a control signal.

26. A system including a plurality of integrated circuit devices, each integrated circuit device of the plurality of integrated circuit devices comprising:

a transmitter to transmit data to a receiving integrated circuit device of the plurality of integrated circuit devices;

a first adjustable delay section to receive a reference clock signal and output a first internal clock signal having a delay with respect to the reference clock signal, wherein the delay is controlled by a control signal;

a first phase detector to receive the reference clock signal and the first internal clock signal and generate the control signal based on a phase difference between the first internal clock signal and the reference clock signal;

a second adjustable delay section to generate a receive clock signal by interpolation such that a phase of the receive clock signal with respect to an external clock signal is based at least in part on the control signal; and

a receiver to sample data, transmitted by a transmitter of another integrated circuit device of the plurality of integrated circuit devices, in response to the receive clock signal.

27. The system of claim 26, wherein each integrated circuit device of the plurality of integrated circuit devices further includes:

a first selection circuit, coupled to the first adjustable delay section, to select a first pair of clock signals from a plurality of clock signals generated by the first adjustable delay section;

first interpolator circuitry, coupled to the second adjustable delay section, to generate a second internal clock signal using the pair of clock signals of the plurality of clock signals such that the phase of the second internal clock signal is interpolated from respective phases of the pair of clock signals based on a phase difference between the external clock signal and a first feedback clock signal, wherein the second internal clock signal is input to the second adjustable delay section;

a third adjustable delay section, coupled to the first interpolator circuitry, to output the first feedback clock signal having a delay with respect to the second internal clock signal that is controlled using the control signal; and

a second phase detector, coupled to the first selection circuit and the first interpolator circuitry, to control the first selection circuit and the first interpolator circuitry based on the phase difference between the external clock signal and the first feedback clock signal.

28. The system of claim 27, wherein at least one integrated circuit device of the plurality of integrated circuit devices further includes:

a fourth adjustable delay section to receive the control signal and generate a transmit clock signal having a phase with respect to the external clock signal that is controlled by the control signal, wherein the transmitter transmits the data in response to the transmit clock signal;

a second selection circuit coupled to the first adjustable delay section to select a second pair of clock signals from the plurality of clock signals generated by the first adjustable delay section;

a third phase detector, coupled to the fourth adjustable delay section and the second selection circuit, to compare the external clock signal with a second feedback clock signal, and control the second selection circuit based on a difference in phase between the external clock signal and the second feedback clock signal;

second interpolator circuitry to generate a third internal clock signal using the second pair of clock signals such that the phase of the third internal clock is interpolated from respective phases of the second pair of clock signals based on the difference in phase between the external clock signal and the second feedback clock signal; and

a fifth adjustable delay section, coupled to the second interpolator circuitry, to receive the third internal clock signal and output the second feedback clock signal having a delay with respect to the third internal clock signal that is controlled using the control signal.

29. The system of claim 26, further including:

a clock generator integrated circuit to generate the external clock signal; and

a clock line coupled to the clock generator integrated circuit and each integrated circuit device of the plurality of integrated circuit device, and wherein the external clock signal propagates on the clock line and is received by each integrated circuit device of the plurality of integrated circuit devices.

30. The system of claim 29, wherein the clock line includes:

a first segment having a first end and a second end, wherein the first end is coupled to the clock generator; and

a second segment having a first end coupled to the second end of the first segment and a second end coupled to a termination element.

31. The system of claim 30, wherein at least one integrated circuit device of the plurality of integrated circuit devices includes:

a transmit clock terminal coupled to the first segment to receive the external clock signal propagating on the first segment, wherein the transmitter transmits the data to the receiving integrated circuit device using the external clock signal received at the transmit clock terminal; and

a receive clock terminal coupled to the second segment to receive the external clock signal propagating on the second segment, wherein the receiver samples the data transmitted by the transmitter of another integrated circuit device using the external clock signal received at the receive clock terminal.

32. The system of claim 26, wherein the transmitter transmits the data to the receiving integrated circuit device such that transitions of the data are in a quadrature alignment with respect to transitions of the external clock signal.

33. The system of claim 26, wherein each integrated circuit device of the plurality of integrated circuit devices receives the external clock signal and generates an internal transmit clock signal using a delay locked loop circuit such that the internal transmit clock signal includes a controlled phase relationship with respect to the external clock signal, wherein the transmitter transmits the data to the receiving integrated circuit device using the transmit clock signal.

34. The system of claim 26, wherein the reference clock signal and the external clock signal are the same clock signal.

35. The system of claim 26, wherein a first integrated circuit device of the plurality of integrated circuit devices is a memory controller device and the other integrated circuit devices of the plurality of integrated circuit devices are integrated circuit memory devices.

36. The system of claim 26 further including a duty cycle correction circuit coupled to the first adjustable delay section to adjust a duty cycle of the reference clock signal.

37. The system of claim 26 wherein the transmitter transmits the data to the receiving integrated device using edges selected from the group consisting of rising and falling edges of the external clock signal.

38. A method of operation in a system including first and second integrated circuit devices, the method comprising:

the first integrated circuit device transmitting data onto a first signal line; and

the second integrated circuit device;

sampling the data from the first signal line in response to transitions of a receive clock signal;

comparing a phase of an external clock signal with the phase of a first feedback clock signal to generate a control signal indicative of a phase difference between the external clock signal and the first feedback clock signal;

generating a first internal clock signal using a first adjustable delay section, wherein the first internal clock signal includes a delay with respect to the external clock signal, wherein the delay is controlled based on the control signal; and

generating the receive clock signal by interpolation using a second adjustable delay section such that a phase of the receive clock with respect to the external clock signal is based at least in part on the control signal.

39. The method of claim 38, further including generating the external clock signal using a clock generator integrated circuit.

40. The method of claim 38, wherein the first integrated circuit device transmits the data such that transitions of the data are in a quadrature alignment with respect to transitions of the external clock signal.

41. The method of claim 38, further including, the first integrated circuit device:

receiving the external clock signal; and

generating an internal transmit clock signal using a delay locked loop circuit such that the internal transmit clock signal includes a controlled phase relationship with respect to the external clock signal, wherein the transmitter transmits the data onto the first signal line using the transmit clock signal.

42. The method of claim 38, wherein the second integrated circuit device uses the external clock signal as the reference clock signal.

43. The method of claim 38, further including:

generating a plurality of clock signals using the first adjustable delay section;

selecting a pair of clock signals from the plurality of clock signals;

comparing a phase of the external clock signal with the phase of a second feedback clock signal to generate a second control signal indicative of a phase difference between the external clock signal and the second feedback clock signal;

generating a second internal clock signal using the pair of clock signals such that the phase of the second internal clock signal is interpolated from respective phases of the pair of clock signals in accordance with the second control signal indicative of the phase difference between the external clock signal and the second feedback clock signal; and

generating the second feedback clock signal using a third adjustable delay section that receives the second internal clock signal, wherein a delay of the second feedback clock signal with respect to the second internal clock signal is controlled in response to the second control signal indicative of the phase difference between the external clock signal and the second feedback clock signal.

44. The method of claim 43, wherein the pair of clock signals are selected according to the difference in phase between the external clock signal and the second feedback clock signal.

45. The method of claim 38, wherein the first integrated circuit device transmits data using edges selected from the group consisting of rising and falling edge transitions of the external clock signal.

46. The method of claim 38, wherein the second integrated circuit device samples the data from the first signal line using edges selected from the group consisting of rising and falling edge transitions of the external clock signal.

47. The method of claim 38, wherein the first integrated circuit device is a memory device including a memory array having memory cells capable of storing the data and wherein the second integrated circuit device is a memory controller device that controls the operation of the first integrated circuit device.

48. An integrated circuit device comprising:

a receiver to sample data from an external signal line in response to a receive clock signal;

a first adjustable delay section to receive a reference clock signal and output a first internal clock signal having a delay with respect to the reference clock signal, wherein the delay is controlled by a control signal;

a first phase detector to receive the reference clock signal and the first internal clock signal and generate the control signal based on a phase difference between the first internal clock signal and the reference clock signal; and

a second adjustable delay section to generate the receive clock signal by interpolation such that a phase of the receive clock signal with respect to an external clock signal is controlled in response to the control signal.

49. The integrated circuit device of claim 48, further including:

a first selection circuit, coupled to the first adjustable delay section, to select a first pair of clock signals from a plurality of clock signals generated by the first adjustable delay section;

first interpolator circuitry, coupled to the second adjustable delay section, to generate a second internal clock signal using the pair of clock signals of the plurality of clock signals such that the phase of the second internal clock signal is interpolated from respective phases of the pair of clock signals based on a phase difference between the external clock signal and a first feedback clock signal, wherein the second internal clock signal is input to the second adjustable delay section;

a third adjustable delay section, coupled to the first interpolator circuitry, to receive the second internal clock signal and output the first feedback clock signal having a delay with respect to the second internal clock signal that is controlled using the control signal; and

a second phase detector, coupled to the first selection circuit and the first interpolator circuitry, to control the first selection circuit and the first interpolator circuitry based on the phase difference between the external clock signal and the first feedback clock signal.

50. The integrated circuit device of claim 49, further including:

a transmitter to transmit data to a receiving integrated circuit device in response to a transmit clock signal;

a fourth adjustable delay section to generate the transmit clock signal having a phase with respect to the external clock signal that is controlled by the control signal;

a second selection circuit coupled to the first adjustable delay section to select a second pair of clock signals from the plurality of clock signals generated by the first adjustable delay section;

a third phase detector, coupled to the fourth adjustable delay section and the second selection circuit, to compare the external clock signal with a second feedback clock signal, and control the second selection circuit based on a difference in phase between the external clock signal and the second feedback clock signal;

second interpolator circuitry to generate a third internal clock signal using the second pair of clock signals such that the phase of the third internal clock is interpolated from respective phases of the second pair of clock signals based on the difference in phase between the external clock signal and the second feedback clock signal; and

a fifth adjustable delay section, coupled to the second interpolator circuitry, to receive the third internal clock signal and output the second feedback clock signal having a delay with respect to the third internal clock signal that is controlled using the control signal.

51. The integrated circuit device of claim 48, further including a transmitter to transmit data to a receiving integrated circuit device.

52. The integrated circuit device of claim 51, wherein the transmitter transmits the data to the receiving integrated circuit device such that transitions of the data are in a quadrature alignment with respect to transitions of the external clock signal.

53. The integrated circuit device of claim 51, wherein the transmitter transmits the data to the receiving integrated device using edges selected from the group consisting of rising and falling edges of the external clock signal.

54. The integrated circuit device of claim 51, further including:

a transmit clock terminal to receive the external clock signal propagating on a first clock line segment, wherein the transmitter transmits the data to the receiving integrated circuit device using the external clock signal received at the transmit clock terminal; and

a receive clock terminal to receive the external clock signal propagating on a second clock line segment, wherein the receiver samples the data transmitted by the transmitter of another integrated circuit device using the external clock signal received at the receive clock terminal.

55. The integrated circuit device of claim 48, wherein the reference clock signal and the external clock signal are the same clock signal.

56. The integrated circuit device of claim 48, further including a duty cycle correction circuit coupled to the first adjustable delay section to adjust a duty cycle of the reference clock signal.

57. The integrated circuit device of claim 48, wherein the receiver samples the data transmitted by the transmitter of another integrated circuit device using edges selected from the group consisting of rising and falling edges of the external clock signal.

58. The integrated circuit device of claim 48, further including a memory array, wherein the integrated circuit device is an integrated circuit memory device.

59. The integrated circuit device of claim 48, wherein the integrated circuit device is a memory controller.

60. The integrated circuit device of claim 48, wherein the integrated circuit device is a microprocessor.

61. The integrated circuit device of claim 48, wherein the integrated circuit device is a graphics engine.

62. An integrated circuit device comprising:

receiver means for sampling data from an external signal line in response to a receive clock signal;

first adjustable delay means for generating a first internal clock signal having a delay with respect to a reference clock signal, wherein the delay is controlled by a control signal;

comparing means for comparing the reference clock signal and the first internal clock signal, to generate the control signal based on a phase difference between the first internal clock signal and the reference clock signal; and

second adjustable delay means for generating the receive clock signal by interpolation such that a phase of the receive clock signal with respect to an external clock signal is controlled in response to the control signal.