Apparatus and method for initiating a sleep state in a system on a chip device
First Claim
1. For use in a data processing system that comprises a system-on-a-chip (SOC) device that comprises a central processing unit and a plurality of system-on-a-chip (SOC) modules, an apparatus for initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said apparatus comprising;
- a power management controller coupled to said central processing unit and to said plurality of SOC modules, said power management controller capable of;
initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal to said central processing unit to cause said central processing unit to enter a sleep state and by sending to each of said plurality of SOC modules a clock disable request signal to cause each of said plurality of SOC modules to enter a sleep state;
receiving a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit had entered a sleep state; and
in response to receiving said suspension request acknowledgement signal from said central processing unit, sending a clock disable request signal to each of said plurality of SOC modules.
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Abstract
An apparatus and method is disclosed for initiating a sleep state in a system-on-a-chip (SOC) device. The apparatus comprises a bus controller coupled to a central processing unit (CPU) and a power management controller that is coupled to the bus controller and to a plurality of SOC modules. The power management controller sends control signals to the bus controller and to the SOC modules to coordinate the shutting down of power to the SOC modules during a process in which the power management controller places the SOC modules of the system-on-a-chip (SOC) device into a sleep state.
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Citations
18 Claims
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1. For use in a data processing system that comprises a system-on-a-chip (SOC) device that comprises a central processing unit and a plurality of system-on-a-chip (SOC) modules, an apparatus for initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said apparatus comprising;
a power management controller coupled to said central processing unit and to said plurality of SOC modules, said power management controller capable of; initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal to said central processing unit to cause said central processing unit to enter a sleep state and by sending to each of said plurality of SOC modules a clock disable request signal to cause each of said plurality of SOC modules to enter a sleep state; receiving a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit had entered a sleep state; and in response to receiving said suspension request acknowledgement signal from said central processing unit, sending a clock disable request signal to each of said plurality of SOC modules. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A data processing system comprising a system-on-a-chip (SOC) device that comprises a central processing unit and a plurality of system-on-a-chip (SOC) modules, said data processing system comprising:
an apparatus or initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said apparatus comprising; a power management controller coupled to said central processing unit and to said plurality of SOC modules, said power management controller capable of; initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal to said central processing unit to cause said central processing unit to enter a sleep state and by sending to each of said plurality of SOC modules a clock disable request signal to cause each of said plurality of SOC modules to enter a sleep state; receiving a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit has entered a sleep state; and in response to receiving said suspension request acknowledgement signal from said central processing unit, sending clock disable request signal to each of said plurality of SOC modules. - View Dependent Claims (9, 10, 11, 12)
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8. The data processing system as set forth in Clam 7 further comprising a bus controller coupled to said central processing unit and to said power management unit, wherein said bus controller comprises a plurality of power management machine specific registers, and wherein said central processing unit is capable of entering information into said plurality of said power management machine specific registers to specify addresses and to specify actions for said power management controller to take when said power management controller executes steps of said initiation of said sleep state in said system-on-a-chip (SOC) device.
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13. For use in a data processing system that comprises a system-on-a-chip (SOC) device that comprises a central processing unit (CPU) and a plurality of system-on-a-chip (SOC) modules, a method for initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said method comprising:
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initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal from a power management controller to said CPU to cause said CPU to enter a sleep state; sending to each of said plurality of SOC modules a clock disable request signal from said power management controller to cause each of said plurality of SOC modules to enter a sleep state; receiving in said power management controller a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit has entered a sleep state; and in response to receiving said suspension request acknowledgement signal from said central processing unit in said power management controller, sending a clock disable request signal from said power management controller to each of said plurality of SOC modules. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification