Apparatus and method for initiating a sleep state in a system on a chip device

• US 7,039,819 B1
• Filed: 04/30/2003
• Issued: 05/02/2006
• Est. Priority Date: 04/30/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kommrusch, Steven J., Landguth, Mark A.
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US10/426,487
• Time in Patent Office: 1,098 Days
• Field of Search: 713300-324
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An apparatus and method is disclosed for initiating a sleep state in a system-on-a-chip (SOC) device. The apparatus comprises a bus controller coupled to a central processing unit (CPU) and a power management controller that is coupled to the bus controller and to a plurality of SOC modules. The power management controller sends control signals to the bus controller and to the SOC modules to coordinate the shutting down of power to the SOC modules during a process in which the power management controller places the SOC modules of the system-on-a-chip (SOC) device into a sleep state.

Claims

1. For use in a data processing system that comprises a system-on-a-chip (SOC) device that comprises a central processing unit and a plurality of system-on-a-chip (SOC) modules, an apparatus for initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said apparatus comprising;

a power management controller coupled to said central processing unit and to said plurality of SOC modules, said power management controller capable of;

initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal to said central processing unit to cause said central processing unit to enter a sleep state and by sending to each of said plurality of SOC modules a clock disable request signal to cause each of said plurality of SOC modules to enter a sleep state;

receiving a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit had entered a sleep state; and

in response to receiving said suspension request acknowledgement signal from said central processing unit, sending a clock disable request signal to each of said plurality of SOC modules.

2. The apparatus as set forth in claim 1 further comprising a bus controller coupled to said central processing unit and to said power management controller, wherein said bus controller comprises a plurality of power management machine specific registers, and wherein said central processing unit is capable of entering information into said plurality of said power management machine specific registers in said bus controller to specify addresses and to specify actions for said power management controller to take when said power management controller executes steps of said initiation of said sleep state in said system-on-a-chip (SOC) device.

3. The apparatus as set forth in claim 1 wherein said power management controller is capable of one of:

(1) waiting to receive an acknowledgement signal from each SOC module of said plurality of SOC modules, said acknowledgement signal from an SOC module acknowledging that a clock disable process in said SOC module has been completed, and (2) waiting for a selected time period and assuming that each SOC module has completed a clock disable process during said selected time period.

4. The apparatus as set forth in claim 3 further comprising an off-chip controller coupled to said power management controller that is capable of sending a sleep request signal to said power management controller, wherein said power management controller, in response to determining that each of said SOC modules has completed a clock disable process, is capable of sending a sleep state acknowledgement signal to said off-chip controller.

5. The apparatus as set forth in claim 4 wherein said power management controller is capable of sending a signal to each SOC module to disable inputs to said SOC module during said initiation of said sleep state of said system-on-a-chip (SOC) device, and said power management controller is capable of sending a signal to gate off all clock signals to each SOC module, and said power management controller is capable of sending a signal to turn off all on-chip phase locked loop circuits and on-chip digital to analog converters.

6. The apparatus as set forth in claim 5 wherein said off-chip controller is capable of sending an external control signal to turn off all system clocks, and is capable of shutting off power to each SOC module of said plurality of SOC modules.

7. A data processing system comprising a system-on-a-chip (SOC) device that comprises a central processing unit and a plurality of system-on-a-chip (SOC) modules, said data processing system comprising:

an apparatus or initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said apparatus comprising;

a power management controller coupled to said central processing unit and to said plurality of SOC modules, said power management controller capable of;

initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal to said central processing unit to cause said central processing unit to enter a sleep state and by sending to each of said plurality of SOC modules a clock disable request signal to cause each of said plurality of SOC modules to enter a sleep state;

receiving a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit has entered a sleep state; and

in response to receiving said suspension request acknowledgement signal from said central processing unit, sending clock disable request signal to each of said plurality of SOC modules.

9. The data processing system as set forth in claim 7 wherein said power management controller is capable of one of:

(1) waiting to receive an acknowledgement signal from each SOC module of said plurality of SOC modules, said acknowledgement signal from an SOC module acknowledging that a clock disable process in said SOC module has been completed, and (2) waiting for a selected time period and assuming that each SOC module has completed a clock disable process during said selected time period.

10. The data processing system as set forth in claim 9 further comprising an off-chip controller coupled to said power management controller that is capable of sending a sleep request signal to said power management controller, wherein said power management controller, in response to determining that each of said SOC modules has completed a clock disable process, is capable of sending a sleep state acknowledgement signal to said off-chip controller.

11. The data processing system as set forth in claim 10 wherein said power management controller is capable of sending a signal to each SOC module to disable inputs to said SOC module during said initiation of said sleep state of said system-on-a-chip (SOC) device, and said power management controller is capable of sending a signal to gate off all clock signals to each SOC module, and said power management controller is capable of sending a signal to turn off all on-chip phase locked loop circuits and on-chip digital to analog converters.

12. The data processing system as set forth in claim 11 wherein said off-chip controller is capable of sending an external control signal to turn off all system clocks, and is capable of shutting off power to each SOC module of said plurality of SOC modules.

8. The data processing system as set forth in Clam 7 further comprising a bus controller coupled to said central processing unit and to said power management unit, wherein said bus controller comprises a plurality of power management machine specific registers, and wherein said central processing unit is capable of entering information into said plurality of said power management machine specific registers to specify addresses and to specify actions for said power management controller to take when said power management controller executes steps of said initiation of said sleep state in said system-on-a-chip (SOC) device.

13. For use in a data processing system that comprises a system-on-a-chip (SOC) device that comprises a central processing unit (CPU) and a plurality of system-on-a-chip (SOC) modules, a method for initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said method comprising:

initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal from a power management controller to said CPU to cause said CPU to enter a sleep state;

sending to each of said plurality of SOC modules a clock disable request signal from said power management controller to cause each of said plurality of SOC modules to enter a sleep state;

receiving in said power management controller a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit has entered a sleep state; and

in response to receiving said suspension request acknowledgement signal from said central processing unit in said power management controller, sending a clock disable request signal from said power management controller to each of said plurality of SOC modules.

14. The method as set forth in claim 13 further comprising:

sending information from said central processing unit to a plurality of power management machine specific registers in a bus controller coupled to said central processing unit and to said power management controller;

said information specifying addresses and actions for said power management controller to take when said power management controller executes steps of said initiation of said sleep state in said s system-on-a-chip (SOC) device.

15. The method as set forth in claim 14 further comprising one of:

said power management controller waiting to receive an acknowledgement signal from each SOC module of said plurality of SOC modules, said acknowledgement signal from an SOC module acknowledging that a clock disable process in said SOC module has been completed;

or

said power management controller waiting for a selected time period and assuming that each SOC module has completed a clock disable process during said selected time period.

16. The method as set forth in claim 15 further comprising:

in response to determining in said bus controller that each of said SOC modules has completed a clock disable process, sending a sleep state acknowledgement signal from said power management controller to an off-chip controller coupled to said power management controller.

17. The method as set forth in claim 16 further comprising:

sending a signal from said power management controller to each SOC module to disable inputs to said SOC module during said initiation of said sleep state of said system-on-a-chip (SOC) device;

sending a signal power said power management controller to gate off au clock signals to each SOC module; and

sending a signal from said power management controller to turn of all on-chip phase locked loop circuits and on-chip digital to analog converters.

18. The method as set forth in claim 17 further comprising:

sending an external control signal from said off-chop controller to turn off all system clocks; and

sending a signal from said off-chip controller to each SOC module of said plurality of SOC modules to shut off power to each SOC module of said plurality of SOC modules.