Integrated circuit with self-testing circuit

• US 7,039,844 B2
• Filed: 01/14/2003
• Issued: 05/02/2006
• Est. Priority Date: 01/17/2002
• Status: Expired due to Term

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hapke, Friedrich
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US10/501,796
• Publication Number:
  US 20050050420A1
• Time in Patent Office: 1,204 Days
• Field of Search: None
• US Class Current: 714/733
• CPC Class Codes: G01R 31/3181 Functional testing G01R31/3177 takes precedence
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

An integrated circuit (14) with an application circuit (1) to be tested and a self-testing circuit (5-13), which is provided for testing the application circuit (1) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates (6, 7, 8) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit (1) for testing purposes, wherein the output signals occurring through the application circuit (1) as a function of the test patterns are evaluated by means of a signature register (13), wherein, by means of second logic gates (10, 11, 12) and signals fed to said gates, those bits of the output signals of the application circuit (1) which, due to the circuit structure of application circuit (1), have undefined states, are blocked during testing.

Claims

1. An integrated circuit comprising;

a test circuit that generates deterministic test vectors;

an application circuit coupled to receive and process the deterministic test vectors to produce output signals;

a logic gate coupled to receive the output signals and block X signal portions of the output signals in response to a first signal and output the remainder of the output signals; and

a signature register coupled to receive the remainder of the output signals and generate a signature.

2. The integrated circuit of claim 1 wherein the X signal comprises an ambiguous signal.

3. The integrated circuit of claim 2 wherein the X signal is ambiguous due to influence by a circuit element in the application circuit which exhibits a storage property.

4. The integrated circuit of claim 2 wherein the X signal is ambiguous due to influence by a circuit element in the application circuit which exhibits an analog behavior.

5. The integrated circuit of claim 1 wherein the test circuit comprises

a test pattern generator for generating pseudorandom test patterns;

and

a second logic gate for receiving the pseudorandom test patterns and modifying the pseudorandom test patterns into a deterministic test patterns in response to a second signal.

6. The integrated circuit of claim 5 wherein the second signal is received from a source external to the integrated circuit.

7. The integrated circuit of claim 5 wherein the test pattern generator is a linear feedback shift register.

8. The integrated circuit of claim 1 wherein the first signal is received from a source external to the integrated circuit.

9. An integrated circuit comprising;

means for generating deterministic test vectors;

means for receiving and processing the deterministic test vectors to produce an output signal;

means for receiving the output signals and a first signal and blocking X signal portions of the output signals in response to the first signal and outputting the remainder of the output signals; and

means for receiving the remainder of the output signals and generating a signature.

10. The integrated circuit of claim 9 wherein the signature indicates if the application circuit is operating correctly.

11. The integrated circuit of claim 9 wherein the X signal comprises an ambiguous signal.

12. The integrated circuit of claim 11 wherein the X signal is ambiguous due to influence by a circuit element in the application circuit which exhibits a storage property.

13. The integrated circuit of claim 11 wherein the X signal is ambiguous due to influence by a circuit element in the application circuit which exhibits an analog behavior.