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Integrated circuit with self-testing circuit

  • US 7,039,844 B2
  • Filed: 01/14/2003
  • Issued: 05/02/2006
  • Est. Priority Date: 01/17/2002
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising;

  • a test circuit that generates deterministic test vectors;

    an application circuit coupled to receive and process the deterministic test vectors to produce output signals;

    a logic gate coupled to receive the output signals and block X signal portions of the output signals in response to a first signal and output the remainder of the output signals; and

    a signature register coupled to receive the remainder of the output signals and generate a signature.

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