Integrated circuit with self-testing circuit
First Claim
1. An integrated circuit comprising;
- a test circuit that generates deterministic test vectors;
an application circuit coupled to receive and process the deterministic test vectors to produce output signals;
a logic gate coupled to receive the output signals and block X signal portions of the output signals in response to a first signal and output the remainder of the output signals; and
a signature register coupled to receive the remainder of the output signals and generate a signature.
4 Assignments
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Accused Products
Abstract
An integrated circuit (14) with an application circuit (1) to be tested and a self-testing circuit (5-13), which is provided for testing the application circuit (1) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates (6, 7, 8) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit (1) for testing purposes, wherein the output signals occurring through the application circuit (1) as a function of the test patterns are evaluated by means of a signature register (13), wherein, by means of second logic gates (10, 11, 12) and signals fed to said gates, those bits of the output signals of the application circuit (1) which, due to the circuit structure of application circuit (1), have undefined states, are blocked during testing.
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Citations
13 Claims
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1. An integrated circuit comprising;
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a test circuit that generates deterministic test vectors; an application circuit coupled to receive and process the deterministic test vectors to produce output signals; a logic gate coupled to receive the output signals and block X signal portions of the output signals in response to a first signal and output the remainder of the output signals; and a signature register coupled to receive the remainder of the output signals and generate a signature. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising;
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means for generating deterministic test vectors; means for receiving and processing the deterministic test vectors to produce an output signal; means for receiving the output signals and a first signal and blocking X signal portions of the output signals in response to the first signal and outputting the remainder of the output signals; and means for receiving the remainder of the output signals and generating a signature. - View Dependent Claims (10, 11, 12, 13)
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Specification