Enhanced turbo product code decoder system utilizing a codeword organization method

• US 7,039,846 B2
• Filed: 05/28/2003
• Issued: 05/02/2006
• Est. Priority Date: 04/04/2000
• Status: Expired due to Term

• Current Assignee: Comtech Telecommunications Corporation
• Original Assignee: Comtech Telecommunications Corporation
• Inventors: Hansen, Tom Leroy, Ladow, Peter Sean, Danielson, Alan Robert, Hewitt, Eric John
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US10/447,717
• Publication Number:
  US 20040010747A1
• Time in Patent Office: 1,070 Days
• Field of Search: 714/755, 714/780, 714/786, 714/752
• US Class Current: 714/755
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/2717 the interleaver involves 3 or more directions
• CPC Class Codes: H03M 13/2721 the interleaver involves a diagonal direction, e.g. by using an interleaving matrix with read-out in a diagonal direction
• CPC Class Codes: H03M 13/2771 Internal interleaver for turbo codes H03M13/2714 and H03M13/2725 take precedence
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2918 with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube
• CPC Class Codes: H03M 13/2921 wherein error correction coding involves a diagonal direction
• CPC Class Codes: H03M 13/2963 Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
• CPC Class Codes: H03M 13/2966 Turbo codes concatenated with another code, e.g. an outer block code
• CPC Class Codes: H03M 13/2975 Judging correct decoding, e.g. iteration stopping criteria
• CPC Class Codes: H03M 13/2981 using as many component decoders as component codes
• CPC Class Codes: H03M 13/451 using a set of candidate code words, e.g. ordered statistics decoding [OSD]
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation
• CPC Class Codes: H03M 13/6513 Support of multiple code types, e.g. unified decoder for LDPC and turbo codes
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H03M 13/6577 Representation or format of variables, register sizes or word-lengths and quantization
• CPC Class Codes: H04L 1/0051 Stopping criteria
• CPC Class Codes: H04L 1/0064 : Concatenated codes
• CPC Class Codes: H04L 1/0066 : Parallel concatenated codes
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178

Abstract

A method and apparatus for decoding a linear block encoded string of information bits comprising: converting the string into a plurality of codewords. Performing hard and soft decisions on each codeword to generate a hard and soft decision vector. Computing the syndrome and finding the location of the two minimum values by Galois Field Arithmetic. Designating these values LOW1 and LOW2 and xoring with a Nc1, thus generating Nc2. Swapping Nc1 with Nc2 and determining the lowest soft decision value, Min1 and a next lowest value, Min2. The two bit locations creating Min1 are designated as MinA and MinB. MinA being replaced with Min2 minus the value MinA. MinB being replaced with Min2 minus the value at MinB. Generating an output codeword by subtracting Min1 from all other bit locations values and 2'"'"'s complementing all soft values with 0 in their location. Creating the new soft value vector. Some embodiments include a system and method that organizes an encoded codeword. The encoded codeword has several codeword bits. The method receives the encoded codeword, assigns multiple codeword bits to at least one memory address in a plurality of memory addresses, and iteratively decodes the received codeword by utilizing the plurality of memory addresses in a predetermined order. The predetermined order is based on a dimension of the received codeword.

Claims

1. A method of organizing an encoded codeword, said encoded codeword having a plurality of codeword bits, said method comprising:

a. receiving the encoded codeword;

b. assigning multiple codeword bits to at least one memory address in a plurality of memory addresses; and

c. iteratively decoding the received codeword by utilizing the plurality of memory addresses in a predetermined order, wherein the predetermined order is based on a dimension of the received codeword.

2. The method of organizing according to claim 1 wherein each of the plurality of memory addresses further comprises a first component and a second component.

3. The method of organizing according to claim 2 wherein the first component is representative of a physical memory, wherein means for decoding associated with the physical memory decodes a unique memory address.

4. The method of organizing according to claim 2 wherein the second component is representative of a physical memory address.

5. The method of organizing according to claim 1 wherein storing the codeword further comprises:

a. reading the codeword in a received order;

b. storing a portion of the codeword bits associated with the at least one memory address;

c. retrieving the portion of the codeword bits for said memory address; and

d. storing a predetermined number of remaining codeword bits associated with the memory address with the retrieved portion of codeword bits.

6. The method of organizing according to claim 1 wherein the predetermined order allows multiple decoders to decode more than one dimension of the codeword independently of one another.

7. The method of organizing according to claim 1 wherein more than one bit in the set of predetermined bits is read by one decoder in a single memory access.

8. The method of organizing according to claim 1 wherein the predetermined order of the plurality of memory addresses are read by a plurality of decoders in a single memory access.

9. The method of organizing according to claim 1 wherein the codeword is a multi-dimensional turbo product code.

10. A decoding system for decoding a plurality of encoded bits in a received codeword, the decoding system comprising:

a. at least one memory module for assigning multiple encoded bits in the codeword to a unique address, wherein the codeword has a plurality of unique addresses; and

b. at least one decoder for decoding the plurality of unique addresses in a predetermined order based on a dimension of the codeword.

11. The decoding system according to claim 10 wherein the at least one memory module further comprises at least one memory bank for storing the set of bits, wherein the at least one memory module reads the set of predetermined bits from the memory bank.

12. The decoding system according to claim 11 wherein the at least one memory bank further comprises an original array memory.

13. The decoding system according to claim 11 wherein the at least one memory bank further comprises a difference array memory.

14. The decoding system according to claim 11 wherein the at least one memory bank further comprises a hard decision array memory.

15. The decoding system according to claim 11 wherein the at least one memory module communicates a set of decoded bits associated with the set of predetermined bits to the memory bank utilizing the unique address of the set of predetermined bits.

16. The decoding system according to claim 10 wherein the codeword is a multi-dimensional turbo product code.

17. The decoding system according to claim 10 wherein the predetermined order allows multiple decoders to decode more than one dimension of the codeword independently of one another.

18. The decoding system according to claim 10 wherein more than one bit in the unique address is read by one decoder in a single memory access.

19. The decoding system according to claim 10 wherein the plurality of unique addresses are read by a plurality of decoders in a single memory access.