Methodology for design of oscillator delay stage and corresponding applications
First Claim
Patent Images
1. A method, comprising:
- A) defining characteristics of an oscillator, said oscillator comprising a series of delay stages, each of said delay stages comprising;
a) at least one differential input;
b) a pair of single ended inverters for each differential input, each pair of single ended inverters further comprising, for their corresponding differential input;
i) a first single ended inverter whose input is coupled to a +input of said corresponding differential input;
ii) a second single ended inverter whose input is coupled to a −
input of said corresponding differential input; and
, c) a differential output, said differential input further comprising;
i) a +output that is coupled to a respective each said second single ended inverter output;
ii) a −
output that is coupled to a respective each output of said first single ended inverter, where said characteristics allow a permissible range of drive strengths for each a respective output of said inverters; and
,B) defining said drive strengths as scaled versions of one another.
7 Assignments
0 Petitions
Accused Products
Abstract
Methods are described that involve characterizing an oscillator'"'"'s jitter or phase noise over a plurality of the oscillator'"'"'s effective number of delay stages. The oscillator comprises a series of delay stages. Each one of the effective number of delay stages, if selected for the oscillator, describes a respective permissible range of inverter drive strengths that may be used within each delay stage of the oscillator to achieve a respective jitter or phase noise characteristic.
23 Citations
94 Claims
-
1. A method, comprising:
-
A) defining characteristics of an oscillator, said oscillator comprising a series of delay stages, each of said delay stages comprising;
a) at least one differential input;
b) a pair of single ended inverters for each differential input, each pair of single ended inverters further comprising, for their corresponding differential input;
i) a first single ended inverter whose input is coupled to a +input of said corresponding differential input;
ii) a second single ended inverter whose input is coupled to a −
input of said corresponding differential input; and
,c) a differential output, said differential input further comprising;
i) a +output that is coupled to a respective each said second single ended inverter output;
ii) a −
output that is coupled to a respective each output of said first single ended inverter,where said characteristics allow a permissible range of drive strengths for each a respective output of said inverters; and
,B) defining said drive strengths as scaled versions of one another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
where; a) for i=0;
ki is the drive strength of each inverter of another pair of single ended inverters between said +output and said −
output, a first inverter of said another pair of single ended inverters having an input coupled to said +output and an output coupled to said −
output, a second inverter of said another pair of single ended inverters having an input coupled to said −
output and an output coupled to said +output;
b) for integers i from 1 to M where M is a number of differential inputs of said at least one differential input;
ki is the drive strength of each inverter of said pair of inverters coupled to ith differential input of said at least one differential input; and
c) for integers i from M+1 to N−
1 where N is a number of delay stages within said series of delay stages (if any such integers exist);
ki=0.
-
-
16. The method of claim 14 wherein said permissible combinations are articulated as a function of an effective number of delay stages (Neff).
-
17. The method of claim 16 wherein said permissible combinations are articulated as a function of Neff according to:
-
where; a) for i=0;
ki is the drive strength of each inverter of another pair of single ended inverters between said +output and said −
output, a first inverter of said another pair of single ended inverters having an input coupled to said +output and an output coupled to said −
output, a second inverter of said another pair of single ended inverters having an input coupled to said −
output and an output coupled to said +output;
b) for integers i=1 to M where M is a number of differential inputs of said at least one differential input;
ki is the drive strength of each inverter of said pair of inverters coupled to ith differential input of said at least one differential input; and
,c) for integers i=M+1 to N−
1 where N is a number of delay stages within said series;
ki=0.
-
-
18. The method of claim 16 wherein said permissible combinations are articulated as a function of Neff according to:
-
wherein N is a number of delay stages, i is integer value, Ki is a drive strength of each inverter, CNeff is a manufacturing related constant and e is a constant.
-
-
19. The method of claim 14 wherein said selecting a specific combination from said permissible combinations further comprises selecting a combination that results in said oscillator having a lower minimum differential mode gain needed for differential mode oscillation than minimum common mode gain needed for common mode oscillation.
-
20. The method of claim 19 wherein said minimum common mode gain needed for common mode oscillation is infinite.
-
21. A method, comprising:
characterizing an oscillator'"'"'s jitter over a plurality of said oscillator'"'"'s effective number of delay stages, said oscillator comprising a series of delay stages, each one of said effective number of delay stages, when selected for said oscillator, to describe a respective permissible range of inverter drive strengths that may be usable within each delay stage of said oscillator to achieve a respective jitter characteristic. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
-
48. A method, comprising:
characterizing an oscillator'"'"'s phase noise over a plurality of said oscillator'"'"'s effective number of delay stages, said oscillator comprising a series of delay stages, each one of said effective number of delay stages, when selected for said oscillator, to describe a respective permissible range of inverter drive strengths that are useable within each delay stage of said oscillator to achieve a respective phase noise characteristic. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74)
-
75. A machine readable medium having stored thereon a sequence of instructions which when executed by a computing system cause said computing system to perform a method, said method comprising:
-
A) defining characteristics of an oscillator, said oscillator comprising a series of delay stages, each of said delay stages comprising;
a) at least one differential input;
b) a pair of single ended inverters for each differential input, each pair of single ended inverters further comprising, for their corresponding differential input;
i) a first single ended inverter whose input is coupled to a +input of said corresponding differential input;
ii) a second single ended inverter whose input is coupled to a −
input of said corresponding differential input; and
,c) a differential output, said differential input further comprising;
i) a +output that is coupled to a respective output of each said second single ended inverter;
ii) a −
output that is coupled to a respective output of each output of said first single ended inverter,where said characteristics allow a permissible range of drive strengths for each of said inverters; and
,B) defining said drive strengths as scaled versions of one another. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94)
where; a) for i=0;
ki is the drive strength of each inverter of another pair of single ended inverters between said +output and said −
output, a first inverter of said another pair of single ended inverters having an input coupled to said +output and an output coupled to said −
output, a second inverter of said another pair of single ended inverters having an input coupled to said −
output and an output coupled to said +output;
b) for integers i from 1 to M where M is a number of differential inputs of said at least one differential input;
ki is the drive strength of each inverter of said pair of inverters coupled to ith differential input of said at least one differential input; and
c) for integers i from M+1 to N−
1 where N is the number of delay stages within said series of delay stages (if any such integers exist);
ki=0.
-
-
90. The machine readable medium of claim 88 wherein said permissible combinations are articulated as a function of an effective number of delay stages (Neff).
-
91. The machine readable medium of claim 90 wherein said permissible combinations are articulated as a function of Neff according to:
-
where; a) for i=0;
ki is the drive strength of each inverter of another pair of single ended inverters between said +output and said −
output, a first inverter of said another pair of single ended inverters having an input coupled to said +output and an output coupled to said −
output, a second inverter of said another pair of single ended inverters having an input coupled to said −
output and an output coupled to said +output;
b) for integers i=1 to M where M is a number of differential inputs of said at least one differential input;
ki is the drive strength of each inverter of said pair of inverters coupled to ith differential input of said at least one differential input; and
,c) for integers i=M+1 to N−
1 where N is the number of delay stages within said series,ki=0.
-
-
92. The machine readable medium of claim 90 wherein said permissible combinations are articulated as a function of Neff according to:
-
wherein N is a number of delay stages, i is integer value, Ki is a drive strength of each inverter, CNeff is a manufacturing related constant and e is a constant.
-
-
93. The machine readable medium of claim 88 wherein said selecting a specific combination from said permissible combinations further comprises selecting a combination that results in said oscillator having a lower minimum differential mode gain needed for differential mode oscillation than minimum common mode gain needed for common mode oscillation.
-
94. The method of claim 93 wherein said minimum common mode gain needed for common mode oscillation is infinite.
Specification