Methods of forming power semiconductor devices having laterally extending base shielding regions

• US 7,041,559 B2
• Filed: 09/08/2004
• Issued: 05/09/2006
• Est. Priority Date: 04/11/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US10/936,757
• Publication Number:
  US 20050032291A1
• Time in Patent Office: 608 Days
• Field of Search: 438/268, 438/138, 438/270, 438/271, 438/273, 438/589
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Methods of forming power semiconductor devices include forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate. A gate electrode is formed on the first surface. Base and base shielding region dopants are implanted into the transition region using the gate electrode as an implant mask. A plurality of annealing steps are performed so that the base shielding region dopants are driven in laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width.

Claims

1. A method of forming a vertical power device, comprising the steps of:

forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate;

forming a gate electrode on the first surface;

implanting base shielding region dopants of second conductivity type at a relatively high dose and high energy level into an upper portion of the transition region, using the gate electrode as an implant mask;

annealing the semiconductor substrate to partially drive the base shielding region dopants vertically into the transition region and laterally underneath the gate electrode and thereby define first and second intermediate shielding regions;

implanting base region dopants of second conductivity type at a relatively low dose and low energy level into the first and second intermediate shielding regions, using the gate electrode as an implant mask;

annealing the semiconductor substrate to drive the base region dopants vertically into the substrate and laterally along the first surface and underneath the gate electrode to thereby define first and second base regions, and simultaneously drive the base shielding region dopants laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width; and

forming first and second source regions in the first and second base regions, respectively.

2. A method of forming a vertical power device, comprising the steps of:

forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate;

forming a gate electrode on the first surface;

implanting base shielding region dopants of second conductivity type at a relatively high dose and high energy level into an upper portion of the transition region, using the gate electrode as an implant mask;

implanting base region dopants of second conductivity type at a relatively low dose and low energy level into the semiconductor substrate, using the gate electrode as an implant mask;

annealing the semiconductor substrate to drive the base region dopants vertically into the substrate and laterally along the first surface and underneath the gate electrode to thereby define first and second base regions, and simultaneously drive the base shielding region dopants laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width; and

forming first and second source regions in the first and second base regions, respectively.