Enhanced substrate contact for a semiconductor device

• US 7,041,561 B2
• Filed: 03/31/2004
• Issued: 05/09/2006
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Xu, Shuming, Baiocchi, Frank A., Shibib, Muhammed Ayman, Jones, Bailey R.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US10/814,062
• Publication Number:
  US 20050221563A1
• Time in Patent Office: 769 Days
• Field of Search: 438/268, 438/269, 438/270, 438/271, 438/589
• US Class Current: 438/270
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A technique for forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench in an upper surface of the semiconductor wafer and partially into the epitaxial layer. The method further includes the step of forming at least one diffusion region between a bottom wall of the trench and the substrate, the diffusion region providing an electrical path between the bottom wall of the trench and the substrate. One or more sidewalls of the trench are doped with a first impurity of a known concentration level so as to form an electrical path between an upper surface of the epitaxial layer and the at least one diffusion region. The trench is then filled with a filler material.

Claims

1. A method of forming a semiconductor structure in a semiconductor wafer, the method comprising the steps of:

forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type;

forming at least one trench in an upper surface of the semiconductor wafer and partially into the epitaxial layer;

forming at least one diffusion region between a bottom wall of the at least one trench and the substrate, the at least one diffusion region providing an electrical path between the bottom wall of the at least one trench and the substrate;

doping at least one or more sidewalls of the at least one trench with a first impurity so as to form an electrical path between an upper surface of the epitaxial layer and the at least one diffusion region; and

substantially filling the at least one trench with a filler material;

wherein the step of doping at least one or more sidewalls of the at least one trench is performed after the step of forming the at least one diffusion region.

2. The method of claim 1, wherein the step of forming the at least one diffusion region comprises the steps of:

implanting the bottom wall of the at least one trench with a second impurity of a known concentration level; and

driving in the second impurity so as to substantially distribute the second impurity between the bottom wall of the at least one trench and the substrate.

3. The method of claim 1, further comprising the steps of:

polishing the upper surface of the epitaxial layer so that the upper surface of the epitaxial layer is substantially planar; and

forming an insulating layer on at least a portion of the upper surface of the epitaxial layer.

4. The method of claim 3, wherein the upper surface of the insulating layer is at least a portion of the upper surface of the semiconductor wafer.

5. The method of claim 1, wherein the step of forming the at least one trench comprises:

forming an insulating layer on at least a portion of the upper surface of the epitaxial layer;

forming at least one opening in the insulating layer corresponding to the at least one trench; and

etching partially into the epitaxial layer.

6. The method of claim 1, wherein the at least one trench comprises a v-groove.

7. The method of claim 1, wherein the step of doping at least one or more sidewalls of the at least one trench with an impurity comprises:

cleaning the sidewalls of the at least one trench to substantially remove any organic material in the at least one trench;

predepositing the first impurity on at least one or more sidewalls of the at least one trench; and

driving in the first impurity.

8. The method of claim 7, wherein the first impurity comprises boron.

9. The method of claim 7, wherein the step of driving in the first impurity comprises heating the semiconductor wafer for a designated period of time.

10. The method of claim 9, wherein the step of heating the semiconductor wafer comprises heating the semiconductor wafer at a temperature in a range of about 900 degrees Celsius to about 1200 degrees Celsius for a duration of about one hour.

11. The method of claim 7, wherein the step of predepositing the first impurity on at least one or more sidewalls of the at least one trench comprises growing an impurity-rich oxide on at least one or more sidewalls of the at least one trench.

12. The method of claim 1, wherein the step of substantially filling the at least one trench comprises depositing a semiconductor material in the at least one trench so as to substantially fill the trench.

13. The method of claim 1, wherein the filler material comprises polysilicon material.

14. The method of claim 1, further comprising the step of forming at least one insulating layer on at least a portion of the upper surface of the epitaxial layer.

15. The method of claim 1, further comprising the step of:

forming an active device in the epitaxial layer proximate the upper surface of the epitaxial layer, the active device being in electrical connection with a first end of the at least one trench, a second end of the at least one trench being electrically connected to the substrate.

16. The method of claim 15, wherein the active device comprises a metal-oxide-semiconductor device.

17. The method of claim 1, further comprising the steps of:

forming an insulating layer on at least a portion of the upper surface of the epitaxial layer;

forming a gate on at least a portion of the insulating layer;

forming source and drain regions of a second conductivity type in the epitaxial layer proximate the upper surface of the epitaxial layer, the source and drain regions being spaced laterally from one another, the gate being formed at least partially between the source and drain regions, the source region being electrically connected to a first end of the at least one trench and a second end of the at least one trench being electrically connected to the substrate.

18. The method of claim 1, wherein the step of forming at least one trench comprises forming a plurality of trenches in the upper surface of the semiconductor wafer and partially into the epitaxial layer, at least two of the trenches being spaced about five microns apart relative to one another.

19. The method of claim 1, wherein the at least one trench is formed less than about 1.2 microns in width.