Device isolation structures of semiconductor devices and manufacturing methods thereof
First Claim
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1. A device isolation structure of a semiconductor device comprising:
- a silicon wafer;
a trench formed in the silicon wafer to have a predetermined depth;
a first thermal oxide layer formed to an inner surface of the trench;
a pad oxide layer formed on the silicon wafer;
a second thermal oxide layer formed on the pad oxide layer, having a round side adjacent to an opening of the trench; and
a field oxide layer filled in the trench having the first thermal oxide layer.
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Abstract
A device isolation structure of a semiconductor device may be a silicon wafer, a trench formed in the silicon wafer to have a predetermined depth, a first thermal oxide layer formed to an inner surface of the trench, a pad oxide layer formed on the silicon wafer, a second thermal oxide layer formed on the pad oxide layer and having a round side adjacent to an opening of the trench, and a field oxide layer filled in the trench having the first thermal oxide layer.
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10 Claims
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1. A device isolation structure of a semiconductor device comprising:
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a silicon wafer; a trench formed in the silicon wafer to have a predetermined depth; a first thermal oxide layer formed to an inner surface of the trench; a pad oxide layer formed on the silicon wafer; a second thermal oxide layer formed on the pad oxide layer, having a round side adjacent to an opening of the trench; and a field oxide layer filled in the trench having the first thermal oxide layer. - View Dependent Claims (2)
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3. A method for manufacturing a device isolation structure of a semiconductor device comprising:
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(A) depositing a pad oxide layer and a pad nitride layer, successively; (B) forming a first photoresist pattern for defining a device isolation region on the pad nitride layer; (C) selectively etching the pad nitride layer using a mask of the photoresist pattern; (D) forming a poly-silicon layer on the entire silicon wafer including the pad nitride layer; (E) forming a second photoresist pattern on the poly-silicon layer for defining a region wider than the device isolation region defined by the first photoresist pattern; (F) back-etching the poly-silicon layer and the silicon wafer using a mask of the second photoresist pattern and the pad nitride layer to form a first trench and a poly stringer; (G) selectively etching the silicon wafer using a mask of the pad nitride layer to form a second trench and to maintain the poly stringer by as much as a predetermined amount to a sidewall of the pad nitride layer, at the same time; (H) oxidizing the second trench and the remaining poly stringer to form a first thermal oxide layer and a second thermal oxide layer; (I) depositing a field oxide layer heavily on the silicon wafer having the first thermal oxide layer and the second thermal oxide layer to fill the second trench; and (J) polishing the field oxide layer by a chemical mechanical polishing (CMP) until a surface of the pad nitride layer are exposed, for the planarization. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10)
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Specification