Adaptive frequency clock generation system

• US 7,042,259 B2
• Filed: 03/31/2004
• Issued: 05/09/2006
• Est. Priority Date: 03/31/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kurd, Nasser A., Barkatullah, Javed S., Madland, Paul
• Primary Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/813,551
• Publication Number:
  US 20050218955A1
• Time in Patent Office: 769 Days
• Field of Search: 327/146, 327/147, 327/154, 327/155, 327/156, 327/162, 327/163, 327/291, 331/17, 331/25, 331/DIG.2, 375/373, 375/375, 375/376
• US Class Current: 327/147
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/22 using more than one loop

Abstract

A clock generating apparatus is provided that includes a first phase lock loop device powered by an analog (or fixed) power supply voltage and a second phase lock loop device powered by the analog power supply voltage and a digital power supply voltage. The second phase lock loop device to output a clock signal having an adaptive frequency based on the digital power supply voltage.

Claims

1. A clock generating apparatus comprising:

a first phase lock loop device to be powered by a first power supply voltage; and

a second phase lock loop device, coupled to the first phase lock loop device, the second phase lock loop device including a bias circuit to be powered by the first power supply voltage and a second power supply voltage and the second phase lock loop device including a voltage controlled oscillator (VCO) to be powered by the second power supply voltage, the bias circuit to provide a bias voltage to the voltage controlled oscillator, the bias voltage being different than the first power supply voltage and the second power supply voltage, the second phase lock loop device to output a clock signal having an adaptive frequency based on the second power supply voltage.

2. The clock generating apparatus of claim 1, wherein the first power supply voltage comprises an analog voltage and the second power supply voltage comprises a digital voltage.

3. The clock generating apparatus of claim 1, wherein fluctuations of the frequency of the clock signal output from the second phase lock loop device are based on fluctuations of the second power supply voltage.

4. The clock generating apparatus of claim 1, wherein the first phase lock loop device outputs a clock signal having a fixed frequency, the clock signal having the fixed frequency being input to the second phase lock loop device.

5. The clock generating apparatus of claim 1, wherein the second phase lock loop device includes components powered by the first power supply voltage and components powered by the second power supply voltage.

6. The clock generating apparatus of claim 1, wherein a sensitivity to droop is based on a coupling percentage of the second power supply voltage to power the VCO.

7. The clock generating apparatus of claim 1, wherein a sensitivity to voltage droop is determined based on a ratio of capacitor sizes within the second phase lock loop device.

8. The clock generating apparatus of claim 1, wherein a sensitivity to voltage droop is determined based on a ratio of transistor sizes within the second phase lock loop device.

9. The clock generating apparatus of claim 1, wherein the apparatus corrects for phase error accumulation.

10. The clock generating apparatus of claim 1, further comprising buffers to couple core components, operating based on the clock signal, with external input/output (I/O).

28. The clock generating apparatus of claim 1, wherein the first power supply voltage is different than the second power supply voltage.

30. The clock generating apparatus of claim 1, wherein the first phase lock loop device includes another bias circuit and another voltage controlled oscillator, the another bias circuit to provide a bias voltage to the another voltage controlled oscillator, the bias voltage being different than the first and second power supply voltages.

11. A clocking system comprising:

an adaptive phase lock loop device powered by an analog power supply voltage and a digital power supply voltage, the adaptive phase lock loop device including a bias circuit to be powered by the analog power supply voltage and the digital power supply voltage, and the adaptive phase lock loop device including a voltage controlled oscillator (VCO) to be powered by the digital power supply voltage, the bias circuit to provide a bias voltage to the voltage controlled oscillator, the bias voltage being different than the analog power supply voltage and the digital power supply voltage, the adaptive phase lock loop device to receive a first clock signal and to output a second clock signal having an adaptive frequency based on a voltage of the digital power supply voltage.

12. The clocking system of claim 11, further comprising a fixed phase lock loop device powered by the analog power supply voltage, the fixed phase lock loop device to receive a reference clock signal and to provide the first clock signal to the adaptive phase lock loop device.

13. The clocking system of claim 12, wherein fluctuations of the frequency of the second clock signal are based on fluctuations of the digital power supply voltage.

14. The clocking system of claim 12, wherein the fixed phase lock loop device outputs the first clock signal having a fixed frequency.

15. The clocking system of claim 11, wherein the adaptive phase lock loop device includes components powered by the analog power supply voltage and components powered by the digital power supply voltage.

16. The clocking system of claim 11, wherein a sensitivity to droop is based on a coupling percentage of the second power supply voltage to power the VCO.

17. The clocking system of claim 11, wherein a sensitivity to voltage droop is determined based on a ratio of capacitor sizes within the adaptive phase lock loop device.

18. The clocking system of claim 11, wherein a sensitivity to voltage droop is determined based on a ratio of transistor sizes within the adaptive phase lock loop device.

19. The clocking system of claim 11, further comprising buffers to couple core components with external input/output (I/0).

20. An electronic system comprising:

an integrated circuit having a clock generating apparatus; and

input/output (I/O) components coupled external to the integrated circuit, the clock generating apparatus comprising;

a first phase lock loop device to be powered by a first power supply voltage; and

a second phase lock loop device to be powered by the first power supply voltage and a second power supply voltage, the second phase lock loop device including a bias circuit to be powered by the first power supply voltage and the second power supply voltage, the second phase lock loop device also including a voltage controlled oscillator to be powered by the second power supply voltage, the bias circuit to provide a bias voltage to the voltage controlled oscillator, the bias voltage being different than the first power supply voltage and the second power supply voltage, the second phase lock loop device to output a clock signal having a frequency based on the second power supply voltage.

21. The electronic system of claim 20, wherein the first power supply voltage comprises an analog voltage and the second power supply voltage comprises a digital voltage.

22. The electronic system of claim 20, wherein fluctuations of the frequency of the clock signal output from the second phase lock loop device are based on fluctuations of the second power supply voltage.

23. The electronic system of claim 20, further comprising buffers to couple core components of the integrated circuit with the I/O components.

24. The electronic system of claim 20, wherein the first power supply and the second power supply are external to the integrated circuit.

25. The electronic system of claim 20, wherein the first power supply voltage is different than the second power supply voltage.

26. The electronic system of claim 20, wherein the first phase lock loop device includes another bias circuit and another voltage controlled oscillator, the another bias circuit to provide a bias voltage to the another voltage controlled oscillator, the bias voltage being different than the first and second power supply voltages.

27. The electronic system of claim 20, further comprising a multiplexer to select an output of the first phase lock loop device or to select the clock signal output from the second phase lock loop device.

29. A clock generating apparatus comprising:

a first phase lock loop device to be powered by a first power supply voltage; and

a second phase lock loop device, coupled to the first phase lock loop device, to be powered by the first power supply voltage and a second power supply voltage, the second phase lock loop device to output a clock signal having an adaptive frequency based on the second power supply voltage; and

a multiplexer to select an output of the first phase lock loop device or to select the clock signal output from the second phase lock loop device.