Method and apparatus for controlling the timing of a communication device
First Claim
1. A system timer for controlling the timing at which a communication device communicates, said system timer comprising:
- a memory device adapted to store a set of software instructions;
a processor coupled to said memory device, said processor being adapted to execute any of said software instructions in any of a plurality of sequences, each of said sequences causing said processor to generate a corresponding set of control signals, each of said corresponding set of control signals being adapted to enable communication by said communication device in one of a multiplicity of communication formats, wherein each of said communication formats devices the timing at which a set of data is communicated by said communication device;
wherein said processor comprises a first processor and further wherein said communication device comprises a second processor, wherein said plurality of sequences in which said first processor executes said software instructions is controlled by said second processor.
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Abstract
A system timer for controlling the timing at which a communication device communications. The system timer can include a memory device and a processor. The memory device can be adapted to store a set of software instructions which can be executed by the processor in any of a plurality of sequences. Each sequence can cause the processor to generate a corresponding set of control signals adapted to enable the communication device to communicate in one of a multiplicity of communication formats. Each communication format can device the timing at which a set of data is communicated by the communication. The plurality of sequences in which the processor executes the software instructions can be controlled by a second processor in the communication device.
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Citations
25 Claims
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1. A system timer for controlling the timing at which a communication device communicates, said system timer comprising:
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a memory device adapted to store a set of software instructions; a processor coupled to said memory device, said processor being adapted to execute any of said software instructions in any of a plurality of sequences, each of said sequences causing said processor to generate a corresponding set of control signals, each of said corresponding set of control signals being adapted to enable communication by said communication device in one of a multiplicity of communication formats, wherein each of said communication formats devices the timing at which a set of data is communicated by said communication device; wherein said processor comprises a first processor and further wherein said communication device comprises a second processor, wherein said plurality of sequences in which said first processor executes said software instructions is controlled by said second processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for controlling the timing at which a communication device communicates, said communication device comprising a first processor and a system timer, said system timer comprising a second processor and a memory device adapted to store a set of software instructions, said method comprising the steps of:
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causing said second processor to execute a set of software instructions in any of a plurality of sequences, each of said sequences causing said second processor to generate a corresponding set of control signals, each of said corresponding set of control signals being adapted to enable communication by said communication device in one of a multiplicity of communication formats, wherein each of said communication formats defines the timing at which a set of data is communicated by said communication device; and
,causing said first processor to define said sequences in which said second processor executes said software instructions. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification