Calibrated data communication system and method

• US 7,042,914 B2
• Filed: 10/13/2003
• Issued: 05/09/2006
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Kim, Jun, Stark, Donald C., Garlepp, Bruno W., Horowitz, Mark A., Donnelly, Kevin S., Yu, Leung, Lau, Benedict Chung-Kwong, Vu, Roxanne, Zerbe, Jared LeVan, Ho, Tsyr-Chyang
• Primary Examiner(s): NGUYEN, BRIAN D
• Application Number:
  US10/684,618
• Publication Number:
  US 20040076192A1
• Time in Patent Office: 939 Days
• Field of Search: 370/451, 370/457, 370/503, 370/706, 370/509, 370/516, 370/517, 370/518, 370/519, 370/252, 365/233, 711/167, 713/400, 713/401
• US Class Current: 370/516
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Claims

1. A method of operation in a system that includes a first integrated circuit device and a second integrated circuit device, the method comprising:

transmitting a data sequence from the first integrated circuit device to the second integrated circuit device;

sampling the data sequence by the second integrated circuit device to produce receiver data;

transmitting the receiver data from the second integrated circuit device to the first integrated circuit device;

performing a comparison, within the first integrated circuit device, between the data sequence and the receiver data; and

based on the comparison, generating information representative of a calibrated timing offset; and

using the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

2. The method of claim 1 further including storing the receiver data in the second integrated circuit.

3. The method of claim 1 further including adjusting transmission timing of the write data by the first integrated circuit based on the information representative of the calibrated timing offset.

4. The method of claim 1 further including adjusting timing of sampling of the write data by the second integrated circuit based on the information representative of the calibrated timing offset.

5. The method of claim 1, wherein the method is performed as part of a calibration sequence.

6. The method of claim 5, wherein the method is performed periodically.

7. The method of claim 5, wherein the method is performed during initialization of the system.

8. The method of claim 1, wherein the calibrated timing offset is an offset relative to a master clock that is received by the second integrated circuit.

9. The method of claim 1, wherein the first integrated circuit is a controller device and the second integrated circuit device is a memory device, and wherein the method further comprises performing write operations to the memory device using the information representative of a calibrated timing offset.

10. The method of claim 1, wherein

said transmitting of the data sequence from the first integrated circuit device to the second integrated circuit device includes transmitting a calibration clock signal that is shifted by about 90°

with respect to main clock signal; and

said method includes transmitting write data from the first integrated circuit to the second integrated circuit in conjunction with transmitting said main clock signal.

11. The method of claim 10, wherein said transmitting, sampling, transmitting and performing a comparison are repeated a plurality of times, using a plurality of different timing offsets, said generating information representative of a calibrated timing offset including identifying a timing offset associated with a change in the receiver data compared with the receiver data at another timing offset.

12. The method of claim 1, wherein said transmitting, sampling, transmitting and performing a comparison are repeated a plurality of times, using a plurality of different timing offsets, said generating information representative of a calibrated timing offset including identifying first and second timing offsets associated with opposing edges of a data eye, and wherein the calibrated timing offset is an offset between the first and second timing offsets.

13. A system comprising a first integrated circuit device and a second integrated circuit device and a signal path connecting the first integrated circuit device to the second integrated circuit device;

the first integrated circuit device including a transmitter configured to transmit a data sequence to the second integrated circuit device;

the second integrated circuit device including a receiver configured to sample the data sequence to produce receiver data, and a transmitter configured to transmit the receiver data to the first integrated circuit device;

wherein the first integrated circuit device is further configured;

to perform a comparison between the data sequence and the receiver data;

based on the comparison, to generate information representative of a calibrated timing offset; and

to use the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

14. The system of claim 13, wherein the second integrated circuit device includes a register to store the calibrated timing offset.

15. The system of claim 14, wherein the second integrated circuit device includes a locked loop circuit to generate a receive clock signal in accordance with the calibrated timing offset stored in the register.

16. The system of claim 13, wherein the first integrated circuit device includes a register to store the calibrated timing offset.

17. The system of claim 16, wherein the first integrated circuit device includes a locked loop circuit to generate a transmit clock signal in accordance with the calibrated timing offset stored in the register.