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Method for quantifying I/O chip/package resonance

  • US 7,043,379 B2
  • Filed: 10/22/2002
  • Issued: 05/09/2006
  • Est. Priority Date: 10/22/2002
  • Status: Active Grant
First Claim
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1. A method for quantifying power supply resonance effects in an integrated circuit, comprising:

  • selecting a plurality of reference voltage potentials for an input buffer on a receiver;

    selecting a plurality of data transmission frequencies for at least one of the plurality of reference voltage potentials;

    transmitting at least one bit pattern to the input buffer for at least one combination of reference voltage potentials selected from the plurality of reference voltage potentials and data transmission frequencies selected from the plurality of data transmission frequencies;

    measuring a voltage potential on the receiver after transmitting the at least one bit pattern; and

    quantifying power supply resonance effects on the integrated circuit based on the measuring.

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