Circuit testing with ring-connected test instruments modules

• US 7,043,390 B2
• Filed: 12/21/2004
• Issued: 05/09/2006
• Est. Priority Date: 08/17/2001
• Status: Expired due to Fees

• Current Assignee: Credence Systems Corporation (COHU Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: Jones, Michael F., Fritzsche, William A., Giral, Frederic
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): SUAREZ, FELIX E
• Application Number:
  US11/021,965
• Publication Number:
  US 20050102592A1
• Time in Patent Office: 504 Days
• Field of Search: 702117-119, 702/121, 702/123, 702/125, 702/186, 702/182, 709/236, 714/124
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence

Abstract

Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Claims

1. A test apparatus comprising a plurality of test instruments synchronized to a global clock and connected to each other through a ring bus, one of the instruments having a programmable device for issuing a trigger signal over the ring bus to the other instruments,

wherein each of the test instruments has a global clock counter that is reset upon receipt of a synchronization signal issued by the global clock, and incremented at each global clock cycle;

and

wherein the trigger signal includes a global clock number and at least one of the other instrument is programmed to be triggered when a difference between its global clock counter and the global clock number is equal to a predetermined value.

2. The test apparatus according to claim 1, wherein the programmable device of the test instrument issuing the trigger signal is programmed to insert the trigger signal onto the ring bus and remove the next empty trigger signal from the ring bus.

3. The test apparatus according to claim 2, wherein the programmable device of the test instrument issuing the trigger signal is programmed to remove the trigger signal inserted by it after the trigger signal has traversed the ring bus one time.

4. The test apparatus according to claim 1, wherein the trigger signal includes the global clock number and a time offset, and at least one of the other instruments is programmed to be triggered when a period of time equal to the time offset has elapsed after a difference between its global clock counter and the global clock number is equal to a predetermined value.

5. The test apparatus according to claim 1, wherein each of the test instruments has a connection to the global clock over which the global clock is supplied.

6. The test apparatus according to claim 5, further comprising a controller that is programmed to issue a synchronization signal to each of the test instruments.

7. The test apparatus according to claim 6, wherein the synchronization signal comprises a global clock with a missing pulse.

8. A test apparatus, comprising:

a main module including a global clock;

a first module synchronized with respect to the global clock and having a global clock counter that is incremented each global clock cycle;

a second module synchronized with respect to the global clock and having a global clock counter that is incremented at each global clock cycle;

a third module synchronized with respect to the global clock and having a global clock counter that is incremented at each global clock cycle; and

a ring bus connecting the first module, the second module, and the third module,

wherein each of the first, second and third modules includes a programmable device that is programmed to;

(i) issue trigger instructions having various trigger types over the ring bus;

(ii) monitor the trigger instructions for a certain trigger type; and

(iii) be triggered by a trigger instruction having said certain trigger type.

9. The test apparatus according to claim 8, wherein each trigger instruction includes a timing value.

10. The test apparatus according to claim 9, wherein the timing value includes a global clock counter number and an offset value, and the first, second and third modules are programmed with a system latency value such that a triggering of at least one of the first, second, and third modules by a trigger instruction occurs when a period of time equal to the offset value plus the system latency value has elapsed after the global clock counter number of the module to be triggered matches the global clock counter number in the trigger instruction.

11. The test apparatus according to claim 8, wherein one of the various trigger types is a global synchronization type.

12. The test apparatus according to claim 8, wherein the programmable device of each test instrument is programmed to insert a trigger instruction onto the ring bus by means of an extra clock stage and remove the next empty trigger instruction from the ring bus.

13. The test apparatus according to claim 12, wherein the programmable device of each test instrument is programmed to remove the trigger instruction inserted by it after the trigger instruction has traversed the ring bus one time.

14. A method of testing an electronic device using an apparatus having a plurality of test instruments connected to each other through a ring bus, comprising the steps of:

synchronizing the test instruments to a global clock;

resetting a global clock counter at each of the test instruments upon synchronization;

incrementing the global clock counter at each of the test instruments at each global clock cycle;

issuing trigger commands over the ring bus;

at each test instrument, receiving the trigger commands over the ring bus and passing on the trigger commands over the ring bus except for the trigger commands originated by said test instrument; and

at each test instrument, supplying test signals to the electronic device with reference to the trigger commands issued for said test instrument and the global clock counter of said test instrument.

15. The method according to claim 14, wherein each trigger command includes a trigger type, a global clock number and an offset value.

16. The method according to claim 15, wherein, at a test instrument that receives a trigger command issued for said test instrument, the test signals are supplied by said test instrument to the electronic device when a period of time equal to the offset value plus a system latency value has elapsed after the global clock counter number of said test instrument matches the global clock counter number in said trigger command.

17. The method according to claim 14, wherein the step of synchronizing includes the step of supplying a global clock with a missing pulse, and the global clock counter at each of the test instruments is reset when the missing pulse is received at each of the test instruments.

18. The method according to claim 14, wherein at least one of the trigger commands is issued by one of the test instruments in response to an internally-derived event or an event detected at the electronic device.

19. The method according to claim 14, further comprising the step of supplying the global clock to each of the test instruments.

20. The method according to claim 14, wherein the step of issuing trigger commands includes the steps of inserting a trigger command onto the ring bus and removing the next empty trigger command from the ring bus, and further comprising the step of generating an error signal if the total number of trigger commands on the ring bus exceeds a maximum number.