Information handling system featuring multi-processor capability with processor located in docking station

• US 7,043,588 B2
• Filed: 05/24/2002
• Issued: 05/09/2006
• Est. Priority Date: 05/24/2002
• Status: Expired due to Term

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Konetski, David
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US10/154,498
• Publication Number:
  US 20030221036A1
• Time in Patent Office: 1,446 Days
• Field of Search: 710/303, 710/304
• US Class Current: 710/303
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations

Abstract

An information handling system—docking station arrangement is disclosed. The information handling system includes a first processor coupled to a main memory and a first docking connector. The docking station includes a second docking connector which mates with the first docking connector of the information handling system. When the information handling system is docked with the docking station, the information handling system interrogates the docking station to determine if a second processor is present in the docking station. If the information handling system detects a second processor in the docking station, then the information handling system switches to a multi-processing mode in which both the first and second processors are employed to process information. However, if the information handling system does not detect a second processor, then the system uses the first processor to process information.

Claims

1. An information handling system comprising:

a first processor;

a first memory coupled to the first processor;

a docking connector, coupled to the first processor, for docking the system to a docking station including a second processor;

a chip including a host controller having a multi-processor handler, coupled to permit the first and second processors to work together in a multi-processor mode in response to the system being docked in the docking station, and to enable the first and second processors to share the first memory via the chip;

in response to the system not being docked in the docking station, the multi-processor handler switching operation of the first processor and the first memory to a single processor mode; and

the docking station including a second memory, the multi-processor handler controlling data communication between the second processor and the second memory in the docking station when the docking connector is docked to the docking station.

2. The information handling system of claim 1 wherein the docking station includes a memory interface to couple the second memory to the second processor.

3. An information handling system docking station combination comprising:

an information handling system including;

a first processor;

a first memory coupled to the first processor;

a first docking connector coupled to the first processor;

a docking station including;

a second processor, the first and second processors being connected by a common core logic chipset and computing architecture; and

a second docking connector, coupled to the second processor, for docking to the first docking connector;

the information handling system further including a chip including a host controller having a multi-processor handler, coupled to permit the first and second processors to work together in a multi-processor mode in response to the system being docked in the docking station, and to enable the first and second processors to share the first memory via the chip;

in response to the system not being docked in the docking station, the multi-processor handler switching operation of the first processor and the first memory to a single processor mode; and

the docking station including a second memory coupled to the second docking connector, the multi-processor handler controlling data communication between the second processor and the second memory in the docking station when the information handling system is docked to the docking station.

4. The information handling system of claim 3 wherein the docking station includes a memory interface to couple the second memory to the second processor.

5. A system comprising:

a docking station for docking with an information handling system including a first processor and a first memory;

a second processor in the docking station;

a docking connector coupled to the second processor to enable multi-processor operation when the information handling system is docked to the docking connector, the first and second processors being connected by a common core logic chipset and computing architecture;

a chip including a host controller having a multi-processor handler coupled to permit the first and second processors to work together in a multi-processor mode in response to the system being docked in the docking station, and to enable the first and second processors to share the first memory via the chip;

in response to the system not being docked in the docking station, the multi-processor handler switching operation of the first processor and the first memory to a single processor mode; and

the docking station including a second memory, the multi-processor handler controlling data communication between the second processor and the second memory in the docking station when the docking connector is docked to the docking station.

6. The system of claim 5 further including a memory interface coupling the second memory to the second processor.

7. A method of operating an information handling system comprising:

providing an information handling system including a first processor coupled to a first memory and to a docking connector;

providing a docking station including a second processor;

providing a chip including a host controller having a multi-processor handler to permit the first and second processors to work together in a multi-processor mode in response to the system being docked in the docking station, and to enable the first and second processors to share the first memory via the chip;

in response to the system not being docked in the docking station, the multi-processor handler switching operation of the first processor and the first memory to a single processor mode; and

providing the docking station with a second memory, the multi-processor handler controlling data communication between the second processor and the second memory in the docking station when the docking connector is docked to the docking station.

8. A method of operating an information handling system comprising:

providing an information handling system including a first processor coupled to a first memory and to a first docking connector;

providing a docking station including a second docking connector which mates with the first docking connector;

connecting the first docking connector to the second docking connector;

detecting, by the information handling system, the presence of a second processor in the docking station if a second processor is present therein, the first and second processors being connected by a common core logic chipset and computing architecture;

providing a chip including a host controller having a multi-processor handler to permit the first and second processors to work together in a multi-processor mode in response to the system being docked in the docking station, and to enable the first and second processors to share the first memory via the chip;

in response to the system not being docked in the docking station, the multi-processor handler switching operation of the first processor and the first memory to a single processor mode; and

the docking station including a second memory, the multi-processor handler controlling data communication between the second processor and the second memory in the docking station when the docking connector is docked to the docking station.