Bus system and bus interface

• US 7,043,589 B2
• Filed: 09/24/2002
• Issued: 05/09/2006
• Est. Priority Date: 09/27/2001
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Chang, Yeow Khai, Zhang, Zhenyu
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US10/253,260
• Publication Number:
  US 20030101298A1
• Time in Patent Office: 1,323 Days
• Field of Search: 710/305, 710 15- 19, 710/46, 710/220, 710/260, 710/267
• US Class Current: 710/305
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus

Abstract

The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station repeatedly sends requests to said second station and the second station responds to the requests. The first station comprises an interruptible processor and a bus interface. The bus interface is operable to interrupt the interruptible processor upon reception of selected responses of the second station. The interruptible processor is operable to handle the interrupts of the bus interface.

Claims

1. A bus system comprising a first station and a second station coupled by a bus for transferring data and control signals, said bus operating according to a protocol in which said first station repeatedly sends requests to said second station and said second station responds to said requests by returning responses over the bus, the returned responses including an ACK response, a NAK response and an error response, said first station including an interruptible processor and a bus interface,

said bus interface being operable for interrupting said interruptible processor in response to the ACK and error responses from said second station, but not interrupting said interruptible processor in response to the NAK response from said second station, and

said interruptible processor is operable to handle the interrupts of said bus interface.

2. A bus system as claimed in claim 1, characterized in that said bus system is a USB bus system.

3. The bus system of claim 2, wherein the error response includes a stall response.

4. The bus system of claim 3, wherein the bus interface includes a host buffer for receiving the requests from the interruptible processor and the bus interface retrieves properties of the requests from the host buffer in a first-in first-out manner and sends the requests to the second station via the bus with no further information required from the interruptible processor.

5. The bus system of claim 4, wherein one of the requests is an IN transfer for polling for data from the second station, the host buffer receives the IN transfer from the interruptible processor and the bus interface retrieves the properties of the IN transfer from the host buffer in the first-in first-out manner and sends the IN transfer to the second station via the bus with no further information required from the interruptible processor, and the bus interface interrupts the interruptible processor in response to a corresponding one of the responses from the second station for the IN transfer unless the corresponding one of the responses is the NAK response.

6. The bus system of claim 5, wherein another one of the requests is an OUT transfer for sending data to the second station, the host buffer receives the OUT transfer from the interruptible processor and the bus interface retrieves the properties of the OUT transfer from the host buffer in the first-in first-out manner and sends the OUT transfer to the second station via the bus with no further information required from the interruptible processor, and the bus interface interrupts the interruptible processor in response to a corresponding one of the responses from the second station for the OUT transfer unless the corresponding one of the responses is the NAK response.

7. A bus interface comprising a connection for a bus and an interrupt output for applying an interrupt to an interruptible processor, characterized in that said bus interface also comprises a controller operable to receive responses including an ACK response, a NAK response and an error response, from said connection and interrupt said processor in response to the ACK and error responses by sending an interrupt signal to the interrupt output, but not interrupt said processor in response to the NAK response.

8. A bus interface for connection to a bus as claimed in claim 7, characterized in that said bus interface is arranged to operate as a USB interface.

9. The bus interface of claim 8, wherein the error response includes a stall response.

10. The bus interface of claim 9, wherein the bus interface further comprises a host buffer for receiving requests from the interruptible processor and the controller retrieves properties of the requests from the host buffer in a first-in first-out manner and transmits the requests to the connection with no further information required from the interruptible processor.

11. The bus interface of claim 10, wherein one of the requests is an IN transfer for polling for data from the connection, the host buffer receives the IN transfer from the interruptible processor and the controller retrieves the properties of the IN transfer from the host buffer in the first-in first-out manner and transmits the IN transfer to the connection with no further information required from the interruptible processor, and the controller sends an interrupt signal to the interrupt output in response to a corresponding one of the responses for the IN transfer unless the corresponding one of the responses is the NAK response.

12. The bus interface of claim 11, wherein another one of the requests is an OUT transfer for sending data to the connection, the host buffer receives the OUT transfer from the interruptible processor and the controller retrieves the properties of the OUT transfer from the host buffer in the first-in first-out manner and transmits the OUT transfer to the connection with no further information required from the interruptible processor, and the controller sends an interrupt signal to the interrupt output in response to a corresponding one of the responses for the OUT transfer unless the corresponding one of the responses is the NAK response.