Reconfigurable memory controller

• US 7,043,611 B2
• Filed: 12/11/2002
• Issued: 05/09/2006
• Est. Priority Date: 12/11/2002
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Delp, Gary S., McClannahan, Gary P., Nation, George W.
• Primary Examiner(s): Elmore, Stephen C.
• Application Number:
  US10/316,510
• Publication Number:
  US 20040117566A1
• Time in Patent Office: 1,245 Days
• Field of Search: 711/154, 711/156, 711/163, 711/170, 326/39
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.

Claims

1. A reconfigurable memory controller, comprising:

a plurality of communicatively coupled memory controllers implemented as configurable logic, wherein the plurality of communicatively coupled memory controllers are reconfigurable so that the memory controllers are configurable into a first memory configuration and reconfigurable into a second memory configuration, the first memory configuration having a different bandwidth grouping than the second memory configuration.

2. The reconfigurable memory controller as described in claim 1, wherein at least one of the plurality of communicatively coupled memory controllers is communicatively coupled to an external memory.

3. The reconfigurable memory controller as described in claim 1, wherein at least one of a width or a depth of a memory array for a first memory controller included in the plurality of memory controllers is different from a second memory controller included in the plurality of memory controllers.

4. The reconfigurable memory controller as described in claim 1, wherein memory operations supported by a first memory controller included in the plurality of memory controllers are different from memory operations supported by a second memory controller included in the plurality of memory controllers.

5. The reconfigurable memory controller as described in claim 1, wherein at least one of a type, or speed of logic interface of a first memory controller included in the plurality of memory controllers is different from a second memory controller included in the plurality of memory controllers.

6. A reconfigurable memory controller, comprising:

a plurality of communicatively coupled memory controllers including a first memory controller, a second memory controller, and a third memory controller, wherein the plurality of communicatively coupled memory controllers are reconfigurable so that the first memory controller and the second memory controller are groupable into a first memory configuration, and the first memory controller and the third memory controller are groupable into a second memory configuration, the first memory configuration being different from the second memory configuration.

7. The reconfigurable memory controller as described in claim 6, wherein at least one of the plurality of communicatively coupled memory controllers is communicatively coupled to an external memory.

8. The reconfigurable memory controller as described in claim 6, wherein at least one of a width or a depth of a memory array for the first memory controller is different from the second memory controller.

9. The reconfigurable memory controller as described in claim 6, wherein memory operations supported by the first memory controller are different than memory operations supported by the second memory controller.

10. The reconfigurable memory controller as described in claim 6, wherein at least one of a type or a speed of logic interface of the first memory controller is different than the second memory controller.

11. A system, comprising:

a reconfigurable memory controller including a plurality of communicatively coupled memory controllers, wherein the plurality of communicatively coupled memory controllers are flexibly configurable so that the memory controllers are configurable into a first memory configuration and reconfigurable into a second memory configuration, the first memory configuration having a different bandwidth grouping than the second memory configuration; and

an external memory communicatively coupled to the reconfigurable memory controller, wherein the reconfigurable memory controller is suitable for controlling operations of the external memory.

12. The system as described in claim 11, wherein the reconfigurable memory controller is communicatively coupled to an external memory.

13. The system as described in claim 11, wherein at least one of a width or a depth of a memory array for a first memory controller included in the plurality of memory controllers is different from a second memory controller included in the plurality of memory controllers.

14. The system as described in claim 11, wherein memory operations supported by a first memory controller included in the plurality of memory controllers are different than memory operations supported by a second memory controller included in the plurality of memory controllers.

15. The system as described in claim 11, wherein at least one of a type, or a speed of logic interface of a first memory controller included in the plurality of memory controllers is different than a second memory controller included in the plurality of memory controllers.

16. A method for reconfiguring a memory controller to support different configurations, comprising:

providing a reconfigurable memory controller having a plurality of communicatively coupled memory controllers, the plurality of memory controllers being groupable;

configuring the plurality of communicatively coupled memory controllers into a first memory configuration, the first memory configuration having a first grouping of memory controllers and a second grouping of memory controllers, the first grouping of memory controllers having a first bandwidth and the second grouping of memory controllers having a second bandwidth; and

reconfiguring the plurality of communicatively coupled memory controllers into a second memory configuration, the second memory configuration having a third grouping of memory controllers and a fourth grouping of memory controllers, the third grouping of memory controllers having a third bandwidth and the fourth grouping of memory controllers having a fourth bandwidth,

wherein the bandwidths as grouped by the first grouping and the second grouping of the first memory configuration are different from the bandwidths of the third grouping and the fourth grouping of the second memory configuration.

17. The method as described in claim 16, wherein the reconfigurable memory controller is communicatively coupled to an external memory.