Method of controlling access to model specific registers of a microprocessor
First Claim
1. A method of controlling accesses to a model specific register of a processor having a normal execution mode and a secure execution mode, said method comprising:
- storing processor information in said model specific register;
protection logic allowing a software invoked write access to modify said information within said model specific register during said normal execution mode;
security logic selectively inhibiting said software invoked write access during said secure execution mode; and
creating a bit map including a plurality of bits each corresponding to a different model specific register, wherein each bit is indicative of whether said corresponding model specific register is protected in a normal kernel mode.
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Abstract
A method of controlling access to a model specific register of a microprocessor. A method of controlling access to a model specific register of a processor having a normal execution mode and a secure execution mode may include storing processor state and mode information in the model specific register. Further, the method may include protection logic allowing a software invoked write access to modify the information within the model specific register during the normal execution mode. The method may further include security logic selectively inhibiting the software invoked write access during the secure execution mode.
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Citations
28 Claims
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1. A method of controlling accesses to a model specific register of a processor having a normal execution mode and a secure execution mode, said method comprising:
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storing processor information in said model specific register; protection logic allowing a software invoked write access to modify said information within said model specific register during said normal execution mode; security logic selectively inhibiting said software invoked write access during said secure execution mode; and creating a bit map including a plurality of bits each corresponding to a different model specific register, wherein each bit is indicative of whether said corresponding model specific register is protected in a normal kernel mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A processor having a normal execution mode and a secure execution mode, said processor comprising:
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execution logic configured to execute code; a model specific register coupled to said execution logic and configured to store processor information; protection logic coupled to said model specific register and configured to allow a software invoked write access to modify said information within said model specific register during said normal execution mode; wherein said protection logic includes security logic configured to selectively inhibit said software invoked write access during said secure execution mode; and wherein said security logic is further configured to access a bit map including a plurality of bits each corresponding to a different model specific register, wherein each bit is indicative of whether said corresponding model specific register is protected in a normal kernel mode. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A computer system comprising:
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a processor having a normal execution mode and a secure execution mode; a memory coupled to said processor and configured to store instructions and data; wherein said processor includes; execution logic configured to execute code; a model specific register coupled to said execution logic and configured to store processor information; protection logic coupled to said model specific register and configured to allow a software invoked write access to modify said information within said model specific register during said normal execution mode; wherein said protection logic includes security logic configured to selectively inhibit said software invoked write access during said secure execution mode; and wherein said security logic is further configured to access a bit map including a plurality of bits each corresponding to a different model specific register, wherein each bit is indicative of whether said corresponding model specific register is protected in a normal kernel mode. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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Specification