Technique for synchronizing clocks in a network

• US 7,043,651 B2
• Filed: 02/19/2002
• Issued: 05/09/2006
• Est. Priority Date: 09/18/2001
• Status: Active Grant

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Felske, Kent E., Montuno, Delfin Y., Ouellette, Michel, Aweya, James
• Primary Examiner(s): Cao, Chun
• Assistant Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US10/076,415
• Publication Number:
  US 20030056136A1
• Time in Patent Office: 1,540 Days
• Field of Search: 713/400, 713/500, 713/600, 713/401, 375/356, 375/326, 375/327, 375/371, 370/516, 370/395.62
• US Class Current: 713/400
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/0664 unidirectional timestamps
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/64322 IP

Abstract

A technique for synchronizing clocks in a network is disclosed. In one exemplary embodiment, the technique may be realized as a method for synchronizing clocks in a network. The method comprises receiving a first timestamp and a second timestamp, each indicating a respective time instance as determined by a first clock signal within the network. The method also comprises measuring a first time interval between the first timestamp and the second timestamp. The method further comprises generating a difference signal representing a difference between the first time interval and a second time interval, and generating a second clock signal based upon the difference signal such that the second clock signal is synchronized with the first clock signal.

Claims

1. A method for synchronizing clocks in a network, the method comprising the steps of:

receiving a first timestamp and a second timestamp each indicating a respective time instance within the network;

delaying the first timestamp by a first delay amount;

measuring a first time interval between the first timestamp delayed by the first delay amount and the second timestamp as determined by a first clock signal;

delaying the first timestamp by a second delay amount;

measuring a second time interval between the first timestamp delayed by the second delay amount and the second timestamp as determined by a second clock signal;

generating a difference signal representing a difference between the first time interval and the second time interval;

filtering the difference signal; and

generating the second clock signal based upon the filtered difference signal such that the second clock signal is synchronized with the first clock signal.

2. The method as defined in claim 1, wherein the first delay amount and the second delay amount are substantially equal delay amounts.

3. The method as defined in claim 1, further comprising the step of:

initializing the difference signal prior to receiving the first timestamp and the second timestamp.

4. The method as defined in claim 1, wherein the step of filtering the difference signal comprises filtering the difference signal with a low pass filter such that the second clock signal is synchronized with the first clock signal based upon the filtered difference signal.

5. The method as defined in claim 4, further comprising the step of:

initializing the filtered difference signal prior to receiving the first timestamp and the second timestamp.

6. The method as defined in claim 1, wherein the step of generating the second clock signal comprises the step of:

controlling the period of a digitally controlled oscillator based upon the filtered difference signal.

7. The method as defined in claim 1, wherein the step of generating the second clock signal comprises the step of:

converting the filtered difference signal from a digital difference signal value into an analog difference signal value; and

controlling the period of a voltage controlled oscillator based upon the analog difference signal value.

8. A computer signal embodied in a readable readable by a computing system and encoding a computer program of instructions for executing a computer process performing the method recited in claim 1.

10. The apparatus as defined in claim 1, wherein the first delay amount and the second delay amount are substantially equal delay amounts.

9. An apparatus for synchronizing clocks in a network, the apparatus comprising:

a receiver for receiving a first timestamp and a second timestamp each indicating a respective time instance within the network; and

a phase-locked loop associated with the receiver, the phase-locked loop comprising;

a first delay element for delaying the first timestamp by a first delay amount;

a first differencing element for measuring a first time interval between the first timestamp delayed by the first delay amount and the second timestamp as determined by a first clock signal;

a second delay element for delaying the first timestamp by a second delay amount;

a second differencing element for measuring a second time interval between the first timestamp delayed by the second delay amount and the second timestamp as determined by a second clock signal;

a third differencing element for generating a difference signal representing a difference between the first time interval and the second time interval;

a filter for filtering the difference signal; and

a variable oscillator for generating the second clock signal based upon the filtered difference signal such that the second clock signal is synchronized with the first clock signal.

11. The apparatus as defined in claim 9, wherein the second differencing element initializes the difference signal prior to receiving the first timestamp and the second timestamp.

12. The apparatus as defined in claim 9, wherein the filter comprises a low pass loop filter for filtering the difference signal such that the second clock signal is synchronized with the first clock signal based upon the filtered difference signal.

13. The apparatus as defined in claim 12, wherein the loop filter initializes the filtered difference signal prior to receiving the first timestamp and the second timestamp.

14. The apparatus as defined in claim 9, wherein the variable oscillator is a digitally controlled oscillator the period of which is controlled based upon the filtered difference signal.

15. The apparatus as defined in claim 9, further comprising:

a digitaltoanalog converter for converting the filtered difference signal from a digital difference signal value into an analog difference signal value, and wherein the variable oscillator is a voltage controlled oscillator the period of which is controlled based upon the analog difference signal value.

16. An article of manufacture for synchronizing clocks in a network, the article of manufacture comprising:

at least one processor readable media; and

instructions carried on the at least one processor readable media;

wherein the instructions are configured to be readable from the at least one processor readable by at least one processor and thereby cause the at least one processor to operate so as to;

receive a first timestamp and a second timestamp each indicating a respective time instance within the network;

delay the first timestamp by a first delay amount;

measure a first time interval between the first timestamp delayed by the first delay amount and the second timestamp as determined by a first clock signal;

delay the first timestamp by a second delay amount;

measure a second time interval between the first timestamp delayed by the second delay amount and the second timestamp as determined by a second clock signal;

generate a difference signal representing a difference between the first time interval and the second time interval;

filter the difference signal; and

generate the second clock signal based upon the filtered difference signal such that the second clock signal is synchronized with the first clock signal.