Redundant clock synthesizer
First Claim
1. A computer system comprising:
- a side plane board;
a first clock board coupled to the side plane board, the first clock board including a first crystal, a first buffer, and a first clock synthesizer circuit, wherein the first clock synthesizer circuit is coupled to receive a first crystal clock signal from the first crystal and provide a first system clock signal to the first buffer; and
a second clock board coupled to the side plane board, the second clock board including a second crystal, a second buffer, and a second clock synthesizer circuit, wherein the second clock synthesizer circuit is coupled to receive a second crystal clock signal from the second crystal and provide a second system clock signal to the second buffer;
wherein each of the first and second clock synthesizer circuits are implemented on a clock synthesizer chip, the clock synthesizer chip including;
a detect/compare circuit, the detect/compare circuit configured to receive a reference clock signal, a feedback clock signal, and a crystal clock signal, wherein the reference clock signal is the system clock signal;
a first multiplexer coupled to receive the crystal clock signal and the reference clock signal;
a second multiplexer coupled to receive the feedback clock signal and a test clock signal;
first and second clock divider circuits each coupled to receive a first output signal from the first and second multiplexers, respectively;
a programmable frequency circuit, wherein the programmable frequency circuit is coupled to provide dividing integers to the first and second clock divider circuits;
a phase locked loop circuit coupled to receive second and third output signals from each of the first and second clock divider circuits;
third and fourth clock divider circuits coupled to receive a fourth output signals, wherein the third clock divider circuit is configured to output the system clock signal and the fourth clock divider circuit is configured to output a test clock signal;
wherein the first clock board is configured to operate as a master and the second clock board is configured to operate as a slave, wherein the first clock synthesizer is configured to determine a phase relationship between the first crystal clock signal and a first feedback clock signal, and wherein the first clock synthesizer is configured to inhibit the first crystal clock signal if the phase relationship exceeds a predetermined limit; and
wherein the second clock board, responsive to detecting the inhibiting of the first crystal clock signal, is configured to act as the master by enabling the second crystal clock signal, wherein the master is configured to provide a master clock signal to the side plane board, wherein the master clock signal is the first system clock signal or the second system clock signal depending upon which of the first or second clock boards is the master.
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Accused Products
Abstract
A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.
49 Citations
24 Claims
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1. A computer system comprising:
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a side plane board; a first clock board coupled to the side plane board, the first clock board including a first crystal, a first buffer, and a first clock synthesizer circuit, wherein the first clock synthesizer circuit is coupled to receive a first crystal clock signal from the first crystal and provide a first system clock signal to the first buffer; and a second clock board coupled to the side plane board, the second clock board including a second crystal, a second buffer, and a second clock synthesizer circuit, wherein the second clock synthesizer circuit is coupled to receive a second crystal clock signal from the second crystal and provide a second system clock signal to the second buffer; wherein each of the first and second clock synthesizer circuits are implemented on a clock synthesizer chip, the clock synthesizer chip including; a detect/compare circuit, the detect/compare circuit configured to receive a reference clock signal, a feedback clock signal, and a crystal clock signal, wherein the reference clock signal is the system clock signal; a first multiplexer coupled to receive the crystal clock signal and the reference clock signal; a second multiplexer coupled to receive the feedback clock signal and a test clock signal; first and second clock divider circuits each coupled to receive a first output signal from the first and second multiplexers, respectively; a programmable frequency circuit, wherein the programmable frequency circuit is coupled to provide dividing integers to the first and second clock divider circuits; a phase locked loop circuit coupled to receive second and third output signals from each of the first and second clock divider circuits; third and fourth clock divider circuits coupled to receive a fourth output signals, wherein the third clock divider circuit is configured to output the system clock signal and the fourth clock divider circuit is configured to output a test clock signal; wherein the first clock board is configured to operate as a master and the second clock board is configured to operate as a slave, wherein the first clock synthesizer is configured to determine a phase relationship between the first crystal clock signal and a first feedback clock signal, and wherein the first clock synthesizer is configured to inhibit the first crystal clock signal if the phase relationship exceeds a predetermined limit; and wherein the second clock board, responsive to detecting the inhibiting of the first crystal clock signal, is configured to act as the master by enabling the second crystal clock signal, wherein the master is configured to provide a master clock signal to the side plane board, wherein the master clock signal is the first system clock signal or the second system clock signal depending upon which of the first or second clock boards is the master. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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a first clock board monitoring a phase difference between a first crystal clock signal and a first feedback clock signal, wherein the first clock board is acting as a master, and wherein the first crystal clock signal is used to generate a system clock signal, the first clock board including a first clock synthesizer circuit; a second clock board receiving the system clock signal and monitoring the system clock signal in reference to a second feedback clock signal, wherein the second clock board is acting as a slave, the second clock board including a second clock synthesizer circuit, wherein each of the first and second clock synthesizer circuits are implemented on a clock synthesizer chip, the clock synthesizer chip including; a detect/compare circuit, the detect/compare circuit configured to receive a reference clock signal, a feedback clock signal, and a crystal clock signal, wherein the reference clock signal is the system clock signal; a first multiplexer coupled to receive the crystal clock signal and the reference clock signal; a second multiplexer coupled to receive the feedback clock signal and a test clock signal; first and second clock divider circuits each coupled to receive a first output signal from the first and second multiplexers, respectively; a programmable frequency circuit, wherein the programmable frequency circuit is coupled to provide dividing integers to the first and second clock divider circuits; a phase locked loop circuit coupled to receive second and third output signals from each of the first and second clock divider circuits; third and fourth clock divider circuits coupled to receive a fourth output signals, wherein the third clock divider circuit is configured to output the system clock signal and the fourth clock divider circuit is configured to output a test clock signal; the first clock board detecting the phase difference exceeding a predetermined limit and inhibiting the first crystal clock signal; the second clock board detecting a plurality of consecutive missing clock edges of the system clock signal; the second clock board enabling a second crystal clock signal responsive to said detecting a plurality of missing edges, wherein the second crystal clock signal, upon enabling, is used to generate a system clock signal, and wherein the second clock board acts as a master when the second crystal clock signal is enabled. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A computer system comprising:
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a plurality of side plane boards; a first clock board coupled to the plurality of side plane boards, the first clock board including a first crystal, a first buffer, and a first clock synthesizer circuit, wherein the first clock synthesizer circuit is coupled to receive a first crystal clock signal from the first crystal and provide a first system clock signal to the first buffer; and a second clock board coupled to the plurality of side plane boards, the second clock board including a second crystal, a second buffer, and a second clock synthesizer circuit, wherein the second clock synthesizer circuit is coupled to receive a second crystal clock signal from the second crystal and provide a second system clock signal to the second buffer; wherein the first clock board is configured to operate as a master and the second clock board is configured to operate as a slave, wherein the first clock synthesizer is configured to determine a phase relationship between the first crystal clock signal and a first feedback clock signal, and wherein the first clock synthesizer is configured to inhibit the first crystal clock signal if the phase relationship exceeds a predetermined limit; and wherein the second clock board, responsive to detecting the inhibiting of the first crystal clock signal, is configured to act as the master by enabling the second crystal clock signal, wherein the master is configured to provide a master clock signal to each of the plurality of side plane boards, wherein the master clock signal is either the first system clock signal or the second system clock signal depending upon which of the first or second clock boards is the master. - View Dependent Claims (23, 24)
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Specification