Piggybacking of ECC corrections behind loads
First Claim
1. An apparatus comprising:
- an error correction code (ECC) check circuit configured to;
detect an ECC error in response to an access to first data in a memory; and
convey a first indication in response to determining said error is located in a first portion of said first data to which said access is not directed; and
a microcode unit coupled to receive an indication that the ECC check circuit has detected the ECC error, wherein the microcode unit is configured to dispatch a first microcode routine configured to correct the ECC error in said first portion.
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Accused Products
Abstract
An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.
89 Citations
22 Claims
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1. An apparatus comprising:
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an error correction code (ECC) check circuit configured to; detect an ECC error in response to an access to first data in a memory; and convey a first indication in response to determining said error is located in a first portion of said first data to which said access is not directed; and a microcode unit coupled to receive an indication that the ECC check circuit has detected the ECC error, wherein the microcode unit is configured to dispatch a first microcode routine configured to correct the ECC error in said first portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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performing an access to first data in a memory; detecting an ECC error in response to the access; and conveying a first indication in response to determining said error is located in a first portion of said first data to which said access is not directed; and dispatching a microcode routine stored by a microcode unit in response to the detecting, wherein the microcode routine includes instructions which, when executed, correct the ECC error in the first portion. - View Dependent Claims (11, 12, 13, 14)
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15. A processor comprising:
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a memory configured to store program data and error correction code (ECC) data corresponding to said program data; and a microcode unit coupled to receive a first indication of an ECC error corresponding to an access of a first data in the memory, said error being located in a first portion of said first data to which said access is not directed, and wherein in response to the first indication, the microcode unit is configured to dispatch a first microcode routine configured to correct the ECC error in said first portion. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification