Method for fabricating ferroelectric random access memory device

• US 7,045,071 B2
• Filed: 12/17/2003
• Issued: 05/16/2006
• Est. Priority Date: 12/30/2002
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Yeom, Seung-Jin, Kweon, Soon-Yong
• Primary Examiner(s): Ahmed, Shamim
• Application Number:
  US10/739,434
• Publication Number:
  US 20040129670A1
• Time in Patent Office: 881 Days
• Field of Search: 216/17, 216/18, 216/22, 216/13, 216/83, 438/715, 252/79.1
• US Class Current: 216/13
• CPC Class Codes: H01L 21/02052 Wet cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/7687 Thin films associated with contacts of capacitors
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

Abstract

The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

Claims

1. A method for fabricating a ferroelectric random access memory device, comprising the steps of:

(a) forming a first inter-layer insulation layer on a substrate providing a transistor;

(b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate;

(c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole;

(d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer;

(e) inducing a predetermined portion of the adhesion layer to be cracked by performing a rapid thermal annealing process, the predetermined portion disposed above an upper part of the plug;

(f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and

(g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

2. The method as recited in claim 1, wherein the plug is made of a conductive material having a thermal expansion coefficient greater than that of the first inter-layer insulation layer.

3. The method as recited in claim 2, wherein the first inter-layer insulation layer is made of a silicon oxide-based material and the plug is formed with one of polysilicon or tungsten.

4. The method as recited in claim 1, wherein the rapid thermal annealing process proceeds at a temperature ranging from about 400°

C. to about 1000 °

C. in an atmosphere of nitrogen (N₂) or argon (Ar) gas.

5. The method as recited in claim 1, wherein the step (f) includes a cleaning process carried out for about 1 minute to about 60 minutes with use of one of a chemical solution SC-1 obtained by mixing ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂) and water (H₂O) in a ratio of about 1 to about 4 to about 20 and a sulfuric acid-peroxide mixture (SPM) solution which is a mixture of H₂SO₄ and H₂O₂.

6. The method as recited in claim 1, wherein the adhesion layer is made of alumina (Al₂O₃), titanium oxide (TiO₂) and tantalum oxide (TaO₂).

7. The method as recited in claim 1, wherein the adhesion layer has a thickness ranging from about 10 Å

to about 500 Å

.

8. The method as recited in claim 1, wherein the step (g) includes the steps of:

forming a conductive layer for use in a bottom electrode on a structure including the exposed barrier metal layer and the adhesion layer;

forming the bottom electrode by etching the conductive layer and the adhesion layer;

forming a second inter-layer insulation layer having a planarized upper surface and encompassing the lower electrode;

forming a ferroelectric layer on the bottom electrode and the second inter-layer insulation layer; and

forming an upper electrode on the ferroelectric layer.

9. The method as recited in claim 1, wherein the step (g) includes the steps of:

forming a first layer for use in a bottom electrode on a structure including the exposed barrier metal layer and the adhesion layer;

etching the first layer and the adhesion layer to form a first stack structure;

forming a second inter-layer insulation layer having a planarized upper surface and encompassing the first stack structure;

sequentially forming a second layer for use in the bottom electrode and a ferroelectric layer on the first stack structure and the second inter-layer insulation layer;

etching the ferroelectric layer and the second layer to form a second stack structure;

forming a third inter-layer insulation layer having a planarized upper surface and encompassing the second stack structure; and

forming an upper electrode on the ferroelectric layer.

10. The method as recited in claim 9, wherein the step of performing a thermal process for crystallizing the ferroelectric layer and removing impurities proceeds before or after the step of forming the upper electrode.

11. The method as recited in claim 9, wherein the first layer is made of a material selected from a group consisting of iridium (Ir), ruthenium titanium nitride (RuTiN), chromium tantalum nitride (CrTaN), chromium titanium nitride (CrTiN) and ruthenium tantalum nitride (RuTaN) and the second layer is formed by stacking a platinum (Pt) layer and an iridium oxide (IrO₂) layer.

12. The method as recited in claim 8, wherein the second inter-layer insulation layer includes double layers having an oxygen barrier layer made of a material selected from a group consisting of alumina (Al₂O₃), silicon nitride (Si₃N₄) and silicon oxynitride (SiON) and an insulation layer made of a material selected from a group consisting of high density plasma (HDP) oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), middle temperature oxide (MTO), high temperature oxide (HTO) and tetraethylorthosilicate (TEOS) oxide or in a single layer including the insulation layer.

13. The method as recited in claim 9, wherein the second inter-layer insulation layer includes double layers having an oxygen barrier layer made of a material selected from a group consisting of Al₂O₃, Si₃N₄ and SiON and an insulation layer made of a material selected from a group consisting of HDP oxide, BPSG, PSG, MTO, HTO and TEOS oxide or in a single layer including the insulation layer.

14. The method as recited in claim 9, wherein the third inter-layer insulation layer includes double layers having an oxygen barrier layer made of a material selected from a group consisting of Al₂O₃, Si₃N₄ and SiON and an insulation layer made of a material selected from a group consisting of HDP oxide, BPSG, PSG, MTO, HTO and TEOS oxide or in a single layer including the insulation layer.