MRAM cell structure and method of fabrication

• US 7,045,368 B2
• Filed: 05/19/2004
• Issued: 05/16/2006
• Est. Priority Date: 05/19/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Applied Spintronics, Inc., Headway Technologies Incorporated
• Inventors: Zhong, Tom, Hong, Liubo, Yang, Lin
• Primary Examiner(s): KENNEDY, JENNIFER M
• Application Number:
  US10/849,311
• Publication Number:
  US 20050260773A1
• Time in Patent Office: 727 Days
• Field of Search: 438/3, 438/240
• US Class Current: 438/3
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/−5 Angstroms.

Claims

1. A method of fabricating an MRAM cell structure having a plurality of MTJ elements each with an uppermost cap layer that has a certain thickness whereby the certain thickness is controlled within a range of about +/−

5 Angstroms, comprising;

(a) providing a plurality of MTJ elements on a substrate and depositing an insulation layer on the substrate to a level that covers the MTJ elements including a top surface of said cap layer;

(b) performing a CMP step to planarize said insulation layer wherein the planarized insulation layer has a first thickness above the top surface of said cap layer; and

(c) performing an etch back step to reduce the thickness of said insulation layer wherein the insulation layer is planarized at a second thickness below the top surface of said cap layer.

2. The method of claim 1 wherein the insulation layer is comprised of silicon oxide or a low k dielectric material and has a thickness of about 800 to 2000 Angstroms above said cap layer before said CMP step.

3. The method of claim 1 wherein said certain thickness above the cap layer is about 60 to 200 Angstroms.

4. The method of claim 1 wherein said second thickness below the top surface of said cap layer is about 50 to 190 Angstroms.

5. The method of claim 1 wherein the cap layer is comprised of Cu, Ru, or a composite layer with an upper Ru layer.

6. The method of claim 5 wherein the cap layer has a certain thickness that is reduced by less than 5 Angstroms during said etch back step.

7. The method of claim 1 wherein etch back step is a plasma etch based on a fluorocarbon chemistry that has a high selectivity between the insulation layer and said cap layer.

8. The method of claim 1 wherein said first thickness is about 250 Angstroms greater than said second thickness.

9. The method of claim 1 wherein the certain thickness of said cap layer is between about 50 and 400 Angstroms.

10. A method for fabricating an MRAM cell structure having a plurality of MTJ elements each with an uppermost cap layer that has a certain thickness whereby the certain thickness is controlled within a range of about +/−

5 Angstroms, comprising;

(a) forming a first conductive layer comprised of a first line on a substrate;

(b) forming a plurality of MTJ elements on said first line, each MTJ having a bottom layer, a free layer on said bottom layer, and a cap layer on said free layer;

(c) depositing an insulation layer on said substrate to a level that covers the MTJ elements including a top surface of said cap layer;

(d) performing a CMP step to planarize said insulation layer wherein the planarized insulation layer a first thickness above the top surface of said cap layer;

(e) performing an etch back step to reduce the thickness of said insulation layer wherein the insulation layer is planarized at a second thickness below the top surface of said cap layer; and

(f) forming a second conductive layer on said insulation layer and cap layer, said second conductive layer is comprised of a second line that contacts the top surface of said cap layer.

11. The method of claim 10 wherein the bottom layer of said MTJ elements is a composite layer comprised of a seed layer on said first line, an AFM layer on the seed layer, a pinned layer on the AFM layer, and a tunnel barrier layer on the pinned layer.

12. The method of claim 10 wherein the first line is comprised of copper and is a bottom electrode, a bit line, or a word line.

13. The method of claim 10 wherein the second line is comprised of copper and is a word line or bit line.

14. The method of claim 10 wherein said first thickness above the cap layer is about 60 to 200 Angstroms.

15. The method of claim 10 wherein said second thickness below the cap layer is about 50 to 190 Angstroms.

16. The method of claim 10 wherein the cap layer has a thickness between about 50 and 400 Angstroms and is comprised of Cu, Ru, or a composite layer with an upper Ru layer.

17. The method of claim 16 wherein said cap layer has a thickness that is reduced by less than 5 Angstroms during said etch back step.

18. The method of claim 10 wherein the MTJ elements have a width from about 0.2 to 0.9 microns.

19. The method of claim 10 wherein the insulation layer is comprised of silicon oxide or a low k dielectric material and has a thickness of about 800 to 2000 Angstroms above said cap layer before said CMP step.

20. The method of claim 10 wherein etch back step is a plasma etch based on a fluorocarbon chemistry that has a high selectivity between the insulation layer and said cap layer.

21. The method of claim 10 wherein said MRAM chip is further comprised of a plurality of MRAM cells that have a distance variation of less than +/−

5 Angstroms from a free layer to an overlying second line after the etch back step.

22. The method of claim 10 wherein the MRAM chip is further comprised of an array of lines in said first conductive layer that are parallel to said first line, an array of lines in the second conductive layer that are parallel to the second line, and an array of MTJs formed at each location where a second line crosses over a first line wherein the distance between a free layer and an overlying second line is maintained to within 10 Angstroms.