Method of forming an electrode with adjusted work function

• US 7,045,406 B2
• Filed: 05/05/2003
• Issued: 05/16/2006
• Est. Priority Date: 12/03/2002
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Tuominen, Marko, Haukka, Suvi, Huotari, Hannu
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): PHAM, THANH V
• Application Number:
  US10/430,703
• Publication Number:
  US 20040106261A1
• Time in Patent Office: 1,107 Days
• Field of Search: 438/198, 438/288, 438/588, 438/591, 438/592, 438/605, 257/407
• US Class Current: 438/198
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method forms a gate stack for a semiconductor device with a desired work function of the gate electrode. The work function is adjusted by changing the overall electronegativity of the gate electrode material in the region that determines the work function of the gate electrode during the gate electrode deposition. The gate stack is deposited by an atomic layer deposition type process and the overall electronegativity of the gate electrode is tuned by introducing at least one pulse of an additional precursor to selected deposition cycles of the gate electrode. The tuning of the work function of the gate electrode can be done not only by introducing additional material into the gate electrode, but also by utilizing the effects of a graded mode deposition and thickness variations of the lower gate part of the gate electrode in combination with the effects that the incorporation of the additional material pulses offers.

Claims

1. A method of fabricating a semiconductor device, comprising

depositing a gate dielectric layer over a semiconductor substrate;

forming a gate electrode comprising a lower part and an upper part over the gate dielectric layer, the gate dielectric layer and the gate electrode forming a gate stack; and

tuning overall electronegativity of the lower part of the gate electrode by adjusting the composition of the lower part of the gate stack to provide a desired work function for the gate stack,

wherein at least the lower part of the gate electrode is formed by an atomic layer deposition (ALD) type process selected from the group consisting of atomic layer deposition (ALD), radical assisted atomic layer deposition (RA-ALD) and plasma enhanced atomic layer deposition (PEALD),

wherein the atomic layer deposition type process comprises one or more deposition cycles comprising a sequence of alternating and repeated exposure of the substrate to two or more different reactants to form an elemental metal film or a compound film of at least binary composition and wherein the work function of the lower part of the gate electrode is tuned by oxygen doping by adjusting the deposition cycles by introducing at least one additional reactant in selected deposition cycles, and wherein the additional reactant comprises an oxygen precursor.

2. The method of claim 1, wherein the oxygen precursor is one of H₂O, O₂, and ozone or a mixture thereof.

3. The method of claim 1, wherein the lower part of the gate electrode is composed of a first material, having a first work function and the upper part of the electrode is composed of a second material, having a second work function, one of the first and second work functions being larger than the desired work function of the gate stack and the other being smaller than the desired work function of the gate stack, the thickness of the lower part of the gate electrode being adjusted such that the gate stack has the desired work function.

4. The method of claim 3, wherein the thickness of the lower part of the gate electrode is 10 nm or less.

5. The method of claim 1, wherein the dielectric layer is hafnium oxide formed by an ALD type process.

6. The method of claim 1, wherein the dielectric layer is formed of hafnium oxide and the lower part of the electrode consists essentially of titanium-aluminum-nitride doped with oxygen.

9. The method of claim 1, wherein the lower part of the electrode is comprised of a conductive diffusion barrier material.

7. A method of fabricating a semiconductor device, comprising

depositing a gate dielectric layer over a semiconductor substrate;

forming a gate electrode comprising a lower part and an upper part over the gate dielectric layer, the gate dielectric layer and the gate electrode forming a gate stack; and

tuning overall electronegativity of the lower part of the gate electrode by adjusting the composition of the lower part of the gate stack to provide a desired work function for the gate stack,

wherein at least the lower part of the gate electrode is formed by an atomic layer deposition (ALD) type process selected from the group consisting of atomic layer deposition (ALD), radical assisted atomic layer deposition (RA-ALD) and plasma enhanced atomic layer deposition (PEALD), and wherein the dielectric layer is formed of hafnium oxide and the lower part of the electrode layer is formed to consist essentially of oxygen-doped transition metal nitride.

8. The method of claim 7, wherein the transition metal nitride is tantalum nitride or titanium nitride.

10. A process for producing a gate stack for a semiconductor device comprising a gate dielectric layer and a gate electrode layer with a lower part and an upper part, the process comprising:

depositing a gate dielectric layer over a substrate;

depositing the lower part of the gate electrode layer over the gate dielectric layer by an ALD type process comprising;

a first process step, wherein 1 to 100 basic deposition cycles are performed to form the lower part of the gate electrode layer;

a second process step, wherein 1 to 100 modified deposition cycles are performed to tune a work function of the gate electrode by adjusting the composition of the lower part of the gate electrode by oxygen doping by introducing an oxygen precursor as an additional reactant in selected deposition cycles; and

repeating the first and the second process steps sequentially and repetitively until a target thickness of the lower part of the gate electrode is reached; and

depositing the upper part of the gate electrode over the lower part,

wherein the target thickness of the lower part of the gate electrode is such that the lower gate electrode composition determines the work function of the gate stack.

11. The process of claim 10, further comprising a step of depositing terminating cycles after depositing the lower part of the gate electrode and prior to depositing the upper part to provide the surface of the lower part of the gate electrode with active surface sites.

12. The process of claim 11, wherein the terminating cycles provides the surface of the lower part of the gate electrode with NH_x or —

OH groups.