Field-effect type semiconductor device for power amplifier

• US 7,045,412 B2
• Filed: 07/26/2004
• Issued: 05/16/2006
• Est. Priority Date: 10/02/2001
• Status: Expired due to Term

• Current Assignee: Tessera Advanced Technologies Inc (Adeia Inc.)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Sugii, Nobuyuki, Yoshida, Isao, Morikawa, Masatoshi, Washio, Katsuyoshi
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/898,257
• Publication Number:
  US 20050003573A1
• Time in Patent Office: 659 Days
• Field of Search: 438/46, 438/47, 438/229, 438/231, 438/232, 438/285, 438/479, 438/761, 438/762, 438/763, 438/779, 438/933
• US Class Current: 438/229
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H03F 3/601 using FET's, e.g. GaAs FET's H03F3/607, H03F3/608 take precedence
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

Claims

1. A method of fabricating a field-effect type semiconductor device, comprising the steps of:

forming a first SiGe layer having a first conductivity-type and high impurity concentration on a major surface of an Si substrate having the first conductivity-type;

forming a second SiGe layer having the first conductivity-type and low impurity concentration on a major surface of said first SiGe layer;

forming an Si layer having low impurity concentration on a major surface of said second SiGe layer, thus completing a semiconductor multi-layer structure;

forming a groove for isolating active regions in a major surface of said semiconductor multi-layer structure;

embedding an insulating material in said groove;

impaling an impurity into said active region;

forming a gate insulating film on a surface of said active region;

forming a gate electrode on said gate insulating film;

forming a drain offset region in said active region in self-alignment with said gate electrode;

forming, in said active region, a drain region being separated from the edge of said gate electrode, contacting said drain offset region in self-alignment with said gate electrode and having an impurity concentration higher than that of said offset region, and a source region in self-alignment with said gate electrode;

exposing said first SiGe layer or said substrate in a region near said source region; and

connecting said exposed portion and said source region by metal or metal silicide.

2. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said first conductivity-type is P-type and said second conductivity-type is N-type.

3. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said first conductivity-type is N-type and said second conductivity-type is P-type.

4. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said first SiGe layer has a thickness of not less than 0.5 μ

m and not greater than 3.0 μ

m.

5. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said second SiGe layer has a thickness of not less than 0.5 μ

m and not greater than 2.5 μ

m.

6. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein a crystal defect region is formed in said Si substrate or said first SiGe layer, and an interface between said first and second SiGe layers and said defect region do not contact each other.

7. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said second SiGe layer has a Ge content ratio of not less than 5% and not greater than 50% and an interface between said first and second SiGe layers has the same Ge content ratio as that of said second SiGe layer.

8. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said first SiGe layer has a Ge content ratio that is small at an interface to said Si substrate and increases in a direction of film thickness.

9. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said Si layer has a thickness of not less than 2 nm and not greater than 70 nm.

10. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said first SiGe layer has a peak value of impurity concentration that is not less than 1×

10¹⁹/cm³.

11. A method of fabricating a field-effect type semiconductor device according to claim 1, wherein said gate electrode includes a polycrystalline Si layer or polycrystalline SiGe layer and a metal silicide layer formed on said polycrystalline Si layer or polycrystalline SiGe layer.