Semiconductor gate structure and method for fabricating a semiconductor gate structure
First Claim
1. A method for fabricating a semiconductor gate structure, comprising:
- depositing a plurality of sacrificial layers on a semiconductor substrate, the plurality at least comprising a sacrificial oxide layer, a doped polysilicon layer and a silicon nitride layer;
patterning the plurality of sacrificial layers to form at least one cutout in the plurality of sacrificial layers for uncovering the semiconductor substrate;
forming a sidewall spacer over sidewalls of the plurality of sacrificial layers in the at least one cutout, a predetermined thickness of the sidewall spacer being set by the dopant concentration of the dopes polysilicon layer;
forming a gate dielectric on the semiconductor substrate in the at least one cutout;
providing a gate electrode in the at least one cutout in the plurality of sacrificial layers; and
removing the plurality of sacrificial layers for uncovering the gate electrode surrounded by the sidewall spacer.
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Accused Products
Abstract
A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.
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Citations
8 Claims
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1. A method for fabricating a semiconductor gate structure, comprising:
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depositing a plurality of sacrificial layers on a semiconductor substrate, the plurality at least comprising a sacrificial oxide layer, a doped polysilicon layer and a silicon nitride layer; patterning the plurality of sacrificial layers to form at least one cutout in the plurality of sacrificial layers for uncovering the semiconductor substrate; forming a sidewall spacer over sidewalls of the plurality of sacrificial layers in the at least one cutout, a predetermined thickness of the sidewall spacer being set by the dopant concentration of the dopes polysilicon layer; forming a gate dielectric on the semiconductor substrate in the at least one cutout; providing a gate electrode in the at least one cutout in the plurality of sacrificial layers; and removing the plurality of sacrificial layers for uncovering the gate electrode surrounded by the sidewall spacer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification