Semiconductor gate structure and method for fabricating a semiconductor gate structure

• US 7,045,422 B2
• Filed: 05/27/2004
• Issued: 05/16/2006
• Est. Priority Date: 05/28/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Schneider, Helmut, Enders, Gerhard, Voigt, Peter
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/854,772
• Publication Number:
  US 20040262697A1
• Time in Patent Office: 719 Days
• Field of Search: 257/388, 257/347, 438/259, 438/291, 438/257
• US Class Current: 438/257
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.

Claims

1. A method for fabricating a semiconductor gate structure, comprising:

depositing a plurality of sacrificial layers on a semiconductor substrate, the plurality at least comprising a sacrificial oxide layer, a doped polysilicon layer and a silicon nitride layer;

patterning the plurality of sacrificial layers to form at least one cutout in the plurality of sacrificial layers for uncovering the semiconductor substrate;

forming a sidewall spacer over sidewalls of the plurality of sacrificial layers in the at least one cutout, a predetermined thickness of the sidewall spacer being set by the dopant concentration of the dopes polysilicon layer;

forming a gate dielectric on the semiconductor substrate in the at least one cutout;

providing a gate electrode in the at least one cutout in the plurality of sacrificial layers; and

removing the plurality of sacrificial layers for uncovering the gate electrode surrounded by the sidewall spacer.

2. The method according to claim 1, wherein the plurality of sacrificial layers is formed from a nitride.

3. The method according to one claim 1, wherein, after patterning the plurality of sacrificial layers, implantation is carried out in the at least one cutout.

4. The method according to either of claim 1, wherein, after patterning the plurality of sacrificial layers, the sacrificial oxide layer is removed in the at least one cutout and the gate dielectric is formed by thermal oxidation.

5. The method according to claim 1, wherein the sidewall spacer is formed at least in two layers from a sidewall oxide and a sidewall oxide spacer.

6. The method according to claim 5, wherein the sidewall oxide and the sidewall oxide spacer is produced by applying a sidewall oxide spacer made of CVD oxide before forming the gate dielectric, a thermal sidewall oxide simultaneously forming below the CVD oxide during formation of the gate dielectric.

7. The method according to claim 1, wherein the gate electrode has metallization which is planarized by CMP planarization, and includes at least one of TiN and W.

8. The method according to claim 1, wherein the plurality of sacrificial layers is removed selectively with respect to the gate electrode and with respect to an underlying gate oxide by anisotropic plasma etching.