Enhancing signal path characteristics in a circuit board

• US 7,045,719 B1
• Filed: 10/21/2002
• Issued: 05/16/2006
• Est. Priority Date: 05/14/2002
• Status: Expired due to Fees

• Current Assignee: Teradata US, Inc. (Teradata Corporation)
• Original Assignee: NCR Corporation
• Inventors: Fan, Jun, Knighten, James L., Alexander, Arthur R.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Norris, Jeremy
• Application Number:
  US10/274,573
• Time in Patent Office: 1,303 Days
• Field of Search: 174262-266, 361761-764, 361/780, 361792-795, 28852-853
• US Class Current: 174/262
• CPC Class Codes: H05K 1/0251 related to vias or transitions between vias and transmission lines
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09327 Special sequence of power, ground and signal layers in multilayer PCB
• CPC Class Codes: H05K 2201/09718 Clearance holes
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to. In another arrangement, clearances around vias at different power reference plane layers are selected to have different sizes to enhance the ability of one of the power reference plane layers (the one with a smaller clearance size) to carry a higher current level.

Claims

1. A circuit board comprising:

a plurality of layers;

a device between two of the plurality of layers,

wherein a first one of the layers containing a power reference plane is provided on a first side of the device, and wherein a second one of the layers containing a power reference plane is provided on a second, opposite side of the device;

a first via passing through the first one the layers;

a second via passing through the second one of the layers;

a first clearance defined around the first via at the first one of the layers; and

a second clearance defined around the second via at the second one of the layers,

wherein the first clearance is larger than the second clearance.

2. The circuit board of claim 1, wherein the plurality of layers further comprise signal layers provided on the first side of the device.

3. The circuit board of claim 2, wherein the first via further passes through the signal layers, the circuit board further comprising a third clearance defined around the first via at the signal layer, the first clearance being larger than the third clearance.

4. The circuit board of claim 3, wherein a third one of the layers containing a power reference plane is also provided on the second side of the device.

5. A circuit board comprising:

plural layers containing power reference planes;

vias passing through the plural layers;

a first clearance defined around a first via at a first one of the plural power reference plane layers, the first clearance having a first size;

a second clearance defined around a second via at a second one of the plural power reference plane layers, the second clearance having a second size different from the first size; and

a device provided between two of the plural power reference plane layers,

wherein at least one power reference plane layer is provided on one side of the device, and at least another power reference plane is provided on another side of the device.

6. The circuit board of claim 5, wherein the first one of the plural power reference plane layers is provided on a first side of the device, and the second one of the plural power reference plane layers is provided on a second, opposite side of the device.

7. The circuit board of claim 6, wherein at least a third one of the power reference plane layers is provided on the second side of the device, a third via passing through the power reference plane third one of the layers,

the circuit board further comprising a third clearance defined around the third via at the third one of the power reference plane layers, the third clearance having generally the second size.

8. A circuit board comprising:

a plurality of layers;

a first via extending through the plurality of layers;

clearances defined around the first via at two or more of the respective layers,

wherein at least one of the clearances has a size that is different from at least another one of the clearances, wherein the different size is selected to set a desired impedance of the first via, and

wherein one of the plurality of layers comprises a signal layer and another one of the plurality of layers comprises a power reference plane layer, wherein the clearance at the signal layer is smaller than the clearance at the power reference plane layer,

a second via extending at least through the signal layer and the power reference plane layer; and

another clearance defined around the second via at the signal layer,

wherein the clearance at the power reference plane layer is defined around both the first and second vias.

9. A circuit board comprising:

a plurality of layers;

a first via extending through the plurality of layers;

clearances defined around the first via at two or more of the respective layers,

wherein at least one of the clearances has a size that is different from at least another one of the clearances, wherein the different size is selected to set a desired impedance of the first via, and

wherein one of the plurality of layers comprises a signal layer and another one of the plurality of layers comprises a power reference plane layer, wherein the clearance at the signal layer is smaller than the clearance at the power reference plane layer; and

a second via extending at least through the power reference plane layer,

wherein the clearance at the power reference plane layer is defined around both the first and second vias.

10. The circuit board of claim 9, further comprising at least another via extending at least through the power reference plane layer,

wherein the clearance at the power reference plane layer is defined around all of the first via, the second via, and the at least another via.

11. A method of making a circuit board comprising:

providing a plurality of layers;

forming a first via through the plurality of layers; and

forming clearances around the via at the respective layers, wherein at least one of the clearances has a size that is different from a size of at least another one of the clearances, wherein providing the plurality of layers comprises providing layers having power reference planes, wherein providing the plurality of layers further comprises providing at least one signal layer, wherein providing a clearance at the signal layer comprises providing a clearance that is smaller than a clearance at one of the layers having a power reference plane, further comprising providing at least another via through the plurality of layers, wherein providing the clearance at one of the layers havinf a power reference plane comprises providing the clearance around all of the first via and the at least another via.