Semiconductor device including a superlattice with regions defining a semiconductor junction

• US 7,045,813 B2
• Filed: 04/01/2005
• Issued: 05/16/2006
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Mears, Robert J., Stephenson, Robert John
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US11/097,433
• Publication Number:
  US 20050167653A1
• Time in Patent Office: 410 Days
• Field of Search: 257/18, 257/14, 257/15, 257/28
• US Class Current: 257/18
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8254 the substrate being a semiconductor, using II-VI technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may further include at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.

Claims

1. A semiconductor device comprising:

a superlattice comprising a plurality of stacked groups of layers;

each group of layers of said superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon;

said energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions; and

said superlattice comprising at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.

2. The semiconductor device of claim 1 wherein said at least one pair of oppositely-doped regions comprises first and second regions in direct contact with one another.

3. The semiconductor device of claim 1 wherein said at least one pair of oppositely-doped regions comprises first and second regions spaced from one another.

4. The semiconductor device of claim 1 wherein said at least one pair of oppositely-doped regions are arranged in a vertical direction so that said at least one semiconductor junction extends in a lateral direction.

5. The semiconductor device of claim 1 wherein said at least one pair of oppositely-doped regions are arranged in a lateral direction so that said at least one semiconductor junction extends in a vertical direction.

6. The semiconductor device of claim 1 wherein each energy band-modifying layer comprises oxygen.

7. The semiconductor device of claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

8. The semiconductor device of claim 1 wherein each energy band-modifying layer is a single monolayer thick.

9. The semiconductor device of claim 1 wherein each base silicon portion is less than eight monolayers thick.

10. The semiconductor device of claim 1 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

11. The semiconductor device of claim 1 wherein all of said base silicon portions are a same number of monolayers thick.

12. The semiconductor device of claim 1 wherein at least some of said base silicon portions are a different number of monolayers thick.

13. A semiconductor device comprising:

a superlattice comprising a plurality of stacked groups of layers;

each group of layers of said superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon;

said energy band-modifying layer comprising at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and

said superlattice comprising at least one pair of oppositely-doped regions therein in direct contact with one another and defining at least one semiconductor junction.

14. The semiconductor device of claim 13 wherein said at least one pair of oppositely-doped regions are arranged in a vertical direction so that said at least one semiconductor junction extends in a lateral direction.

15. The semiconductor device of claim 13 wherein said at least one pair of oppositely-doped regions are arranged in a lateral direction so that said at least one semiconductor junction extends in a vertical direction.

16. The semiconductor device of claim 13 wherein each energy band-modifying layer is a single monolayer thick.

17. The semiconductor device of claim 13 wherein each base silicon portion is less than eight monolayers thick.

18. The semiconductor device of claim 13 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

19. The semiconductor device of claim 13 wherein all of said base silicon portions are a same number of monolayers thick.

20. The semiconductor device of claim 13 wherein at least some of said base silicon portions are a different number of monolayers thick.