Memory cell and method for forming the same
First Claim
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1. A plurality of memory cells formed on a surface of a substrate, comprising:
- an active region formed in the substrate;
a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;
a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;
a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and
a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region.
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Abstract
A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.
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Citations
25 Claims
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1. A plurality of memory cells formed on a surface of a substrate, comprising:
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an active region formed in the substrate; a plurality of posts formed on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions; a plurality of contacts formed over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts; a plurality of memory cell capacitors formed on a respective one of the plurality of posts; and a plurality of gate structures formed adjacent a respective one of the plurality of posts to provide a respective vertical transistor configured to electrically couple the respective memory cell capacitor to the active region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory cell structure formed on a substrate having a surface, comprising:
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an active region formed in the substrate; a semiconductor post formed on the active region; first and second contacts formed on the active region and on laterally disposed on opposite sides of the semiconductor post along the surface of the substrate; a memory cell capacitor formed on the semiconductor post; and a vertical access transistor having a gate formed adjacent the semiconductor post and configured to electrically couple the capacitor to the first and second contacts in response to being activated. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification