Termination for trench MIS device having implanted drain-drift region

• US 7,045,857 B2
• Filed: 03/26/2004
• Issued: 05/16/2006
• Est. Priority Date: 03/26/2004
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Chen, Qufei, Darwish, Mohamed N., Qi, Jainhai, Terrill, Kyle W.
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US10/810,031
• Publication Number:
  US 20050215011A1
• Time in Patent Office: 781 Days
• Field of Search: 257330-334, 257/520
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Claims

1. A semiconductor die containing an MIS device, said die comprising a first layer of a first conductivity type overlying a second layer of a second conductivity type opposite to said first conductivity type, said die further comprising:

an active area comprising an MIS device, said MIS device comprising;

an active trench comprising a conductive gate material and extending downward from a surface of said first layer, a bottom of said active trench being located in said first layer;

a source region of said second conductivity type in said first layer, said source region being located adjacent said surface of said die and a sidewall of said active trench; and

a drain-drift region of said second conductivity type extending downward from said bottom of said active trench to said second layer; and

a termination region comprising;

at least a first and a second termination trench, each of said termination trenches extending downward from said surface of said die, each of said termination trenches comprising a conductive material and having a bottom in said first layer, said conductive material in each of said termination trenches being insulated from said first layer by a dielectric layer lining the sidewalls and bottom of said termination trench;

a region of said second conductivity type extending from a bottom of each of said termination trenches to said second layer;

at least a first and a second metal layer above said surface of said die, said first metal layer being electrically connected to said conductive material in said first termination trench and to a portion of said first layer in a mesa between said first and second trenches, said second metal layer being electrically connected to said conductive material in said second termination trench and to a portion of said first layer in a region on a side of said second termination trench opposite from said mesa, wherein said conductive materials in said termination trenches are electrically isolated from each other and from said source region and said first layer.

2. The semiconductor die of claim 1 wherein the conductive material in the first and second termination trenches is allowed to float electrically.

3. The semiconductor die of claim 1 wherein the second layer comprises a substrate and a first epitaxial layer overlying said substrate.

4. The semiconductor die of claim 3 wherein the first layer comprises a second epitaxial layer of the first conductivity type formed on top of the first epitaxial layer.

5. The semiconductor die of claim 1 wherein said conductive material comprises polysilicon.

6. The semiconductor die of claim 1 wherein said dielectric layer lining each of said termination trenches comprises a thick portion at bottom of said trench.

7. The semiconductor die of claim 1 comprising first and second contact regions of said second conductivity at said surface of first layer, said first and second contact regions being doped with a dopant of said first conductivity type to a doping concentration greater than a doping concentration of said first layer, said first contact region being located adjacent an interface between said first metal layer and said first layer, said second contact region being located adjacent an interface between said second metal layer and said first layer.