Semiconductor device of reduced gate overlap capacitance and method of manufacturing the semiconductor device

• US 7,045,867 B2
• Filed: 06/09/2003
• Issued: 05/16/2006
• Est. Priority Date: 09/18/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Maeda, Shigenobu, Matsumoto, Takuji, Hirano, Yuuichi, Dang, Hai
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US10/456,548
• Publication Number:
  US 20040051151A1
• Time in Patent Office: 1,072 Days
• Field of Search: 257/288, 257/344, 257/408, 257/412
• US Class Current: 257/408
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4×10¹⁸ cm⁻³±40%.

Claims

1. A semiconductor device including an MOS transistor comprising:

a semiconductor substrate;

a gate insulating film selectively disposed on said semiconductor substrate;

a gate electrode selectively disposed on said gate insulating film; and

a spacer insulating film disposed on a side surface of said gate electrode,

wherein said gate insulating film includes a first part corresponding to a central portion of a lower part of said gate electrode and a second part corresponding to an edge portion of the lower part of said gate electrode,

said second part has a contoured shape widening vertically so as to increase its thickness from a portion for engagement with said first part,

a contoured shape in a state that said spacer insulating film engages said second part of said gate insulating film is in a continuous form of at least an inclination having a first angle corresponding to a tilt angle of a side lower part of said gate electrode and an inclination having a second angle with respect to a main surface of said semiconductor substrate on an upper side of said second part of said gate insulating film,

said first angle is greater than said second angle, and

the side surface of said gate electrode has a contoured shape curved in a continuous form such that an upper main surface of said gate electrode is wider than a lower main surface.

2. The semiconductor device according to claim 1, wherein

said first angle is in a range of 86°

±

5%, and

said second angle is in a range of 10°

±

70%.

3. The semiconductor device according to claim 1 wherein

said MOS transistor has a source/drain layer extending to an underside of said second part of said gate insulating film, and

an impurity concentration of said source/drain layer is in a range of 4×

10¹⁸ cm<sup>−

3</sup>±

40%.

4. The semiconductor device according to claim 3 wherein

said MOS transistor further includes an elevated source/drain electrode disposed above a portion of said source/drain layer which extends into a main surface of said semiconductor substrate located externally of the side surface of said gate electrode.

5. A semiconductor device including an MOS transistor comprising:

a semiconductor substrate;

a gate insulating film selectively disposed on said semiconductor substrate;

a gate electrode selectively disposed on said gate insulating film; and

a spacer insulating film disposed on a side surface of said gate electrode,

wherein said gate insulating film includes a first part corresponding to a central portion of a lower part of said gate electrode and a second part corresponding to an edge portion of the lower part of said gate electrode,

said second part has a contoured shape widening upwardly so as to increase its thickness from a portion for engagement with said first part and also curving so as to project outwardly.

6. The semiconductor device according to claim 5, wherein

said second part of said gate insulating film includes a curvature of approximately a circle.

7. The semiconductor device according to claim 5 wherein

said MOS transistor has a source/drain layer extending to an underside of said second part of said gate insulating film, and

an impurity concentration of said source/drain layer is in a range of 1×

10¹⁹ cm<sup>−

3</sup>±

40%.

8. The semiconductor device according to claim 7 wherein

said MOS transistor further includes an elevated source/drain electrode disposed above a portion of said source/drain layer which extends into a main surface of said semiconductor substrate located externally of the side surface of said gate electrode.

9. The semiconductor device according to claim 5, wherein

said gate electrode is a metal gate.