Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board

• US 7,045,901 B2
• Filed: 02/21/2003
• Issued: 05/16/2006
• Est. Priority Date: 05/19/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Peng, Bryan
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/371,505
• Publication Number:
  US 20030127749A1
• Time in Patent Office: 1,180 Days
• Field of Search: 257777-779, 257/772, 257/786, 257/734, 257/737, 257/738, 257/723, 257/685, 257/686, 257/680, 257/774, 257431-433, 257/668, 257/784, 361/761, 361/764, 361/748, 361/803
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Claims

1. A method of forming a chip package for semiconductor chips including the steps as follows:

forming a printed circuit board (PCB6) with an open window hole (W) therethrough, the printed circuit board (PCB6) having a length and a width and a top surface and a bottom surface and the open window hole (W) having a greater length than width,

forming semiconductor chips including a primary chip (CH5) and a secondary chip (CH6),

the primary chip (CH5) and the secondary chip (CH6) each having a length greater than the width of the open window hole (W),

forming bonded connections (SB) between the top surface of the printed circuit board (PCB6) and the primary chip (CH5), with the primary chip (CH5) overlying the open window hole (W) and with the primary chip (CH5) extending transversely across the width of the open window hole (W), and

locating the secondary chip (CH6) suspended within the open window hole (W) and forming bonded connections (SB) between the secondary semiconductor chip (CH6) and the primary chip (CH5) in a chip-on-chip connection.

2. The method of claim 1 including the primary chip (CH5) and the secondary chip (CH6) having substantially equal chip lengths and substantially equal chip widths.

3. The method of claim 1 including forming the bonded connections of the chips (CH5/CH6) to the printed circuit board (PCB6) and the other chip (CH5/CH6) by means selected from the following:

a) solder balls, and

b) gold bumps.

4. The method of claim 1 including:

forming the bonded connections of the chips to the printed circuit board (PCB6) by means selected from the following;

a) solder balls, and

b) gold bumps, and

forming big solder balls on the top surface of the printed circuit board (PCB6),

the open window hole (W) having a width less than the length, and

the primary chip (CH5) and the secondary chip (CH6) having substantially equal chip lengths and substantially equal chip widths.

5. A chip package for semiconductor chips including:

a printed circuit board (PCB6) with an open window hole (W) therethrough, the printed circuit board (PCB6) having a length and a width and a top surface and a bottom surface,

semiconductor chips including a primary chip (CH5) and a secondary chip (CH6),

the primary chip (CH5) and the secondary chip (CH6) each having a length greater than the width of the open window hole (W),

bonded connections (SB) between the top surface of the printed circuit board (PCB6) and the primary chip (CH5), with the primary chip (CH5) overlying the open window hole (W) and with the primary chip (CH5) extending transversely across the width of the open window hole (W),

the secondary chip (CH6) being suspended within the open window hole (W) and having bonded connections (SB) between the secondary semiconductor chip (CH6) and the primary chip (CH5) in a chip-on-chip connection.

6. The package of claim 5 including the primary chip (CH5) and the secondary chip (CH6) having substantially equal chip lengths and substantially equal chip widths.

7. The package of claim 5 including bonded connections of the chips (CH5/CH6) to the printed circuit board (PCB6) and the other chip (CH5/CH6) by means selected from the following:

a) solder balls, and

b) gold bumps.

8. The package of claim 5 including bonded connections of the chips (CH5/CH6) to the printed circuit board (PCB6) and the other chip (CH5/CH6) by means selected from the following:

a) solder balls, and

b) gold bumps, and

big solder balls formed on the top surface of the printed circuit board (PCB6),

the open window hole (W) having a width less than the length,

the primary chip (CH5) and the secondary chip (CH6) having substantially equal chip lengths and substantially equal chip widths.