Upward and downward pulse stretcher circuits and modules

• US 7,046,038 B2
• Filed: 01/03/2003
• Issued: 05/16/2006
• Est. Priority Date: 08/03/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Porter, John D., Weber, Larren G., Gans, Dean D.
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): MAI, LAM T
• Application Number:
  US10/336,386
• Publication Number:
  US 20030102896A1
• Time in Patent Office: 1,229 Days
• Field of Search: 326/82, 326/26, 326/27
• US Class Current: 326/82
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

Claims

1. A downward pulse stretcher circuit for widening a downward pulse comprising:

a skewed inverter rising logic device including a first feedback delay for receiving a downward pulse input signal, said downward pulse input signal having a first pulse width and transmitting an intermediate pulse signal resulting at least in part from said first feedback delay; and

a skewed inverter falling logic device including a second feedback delay for receiving said intermediate pulse signal and outputting a downward pulse output signal having a second pulse width and resulting at least in part from said second feedback delay, said second pulse width being wider than said first pulse width.

2. A downward pulse stretcher module for selectively widening a downward pulse input signal comprising a selectable number n of downward pulse stretcher circuits connected in series, each downward pulse stretcher circuit comprising:

a skewed inverter rising logic device including a first feedback delay for receiving a downward pulse input signal, said downward pulse input signal having a first pulse width and transmitting an intermediate pulse signal resulting at least in part from said first feedback delay; and

a skewed inverter falling logic device including a second feedback delay for receiving said intermediate pulse signal and outputting a downward pulse output signal having a second pulse width and resulting at least in part from said second feedback delay, said second pulse width being wider than said first pulse width.

3. An upward pulse stretcher circuit for widening an upward pulse comprising:

a skewed inverter falling logic device including a first feedback delay for receiving an upward pulse input signal, said upward pulse input signal having a first pulse width and transmitting an intermediate pulse signal resulting at least in part from said first feedback delay; and

a skewed inverter rising logic device including a second feedback delay for receiving said intermediate pulse signal and outputting an upward pulse output signal having a second pulse width and resulting at least in part from said second feedback delay, said second pulse width being wider than said first pulse width.

4. An upward pulse stretcher module for selectively widening an upward pulse input signal comprising a selectable number n of upward pulse stretcher circuits, each upward pulse stretcher circuit comprising:

a skewed inverter falling logic device including a first feedback delay for receiving an upward pulse input signal, said upward pulse input signal having a first pulse width and transmitting an intermediate pulse signal resulting at least in part from said first feedback delay; and

a skewed inverter rising logic device including a second feedback delay for receiving said intermediate pulse signal and outputting an upward pulse output signal having a second pulse width and resulting at least in part from said second feedback delay, said second pulse width being wider than said first pulse width.